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drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init

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Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also
need REG_A6XX_GBIF_HALT to be set to 0.

This is typically done automatically on successful GX collapse, but in
case that fails, we should take care of it.

Also, add a memory barrier to ensure it's gone through before jumping
to further initialization.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542760/
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Konrad Dybcio 2023-06-16 01:20:50 +02:00 committed by Rob Clark
parent 277b967829
commit 05a23a76d3
1 changed files with 5 additions and 1 deletions
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6
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
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@ -1111,8 +1111,12 @@ static int hw_init(struct msm_gpu *gpu)
a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
/* Clear GBIF halt in case GX domain was not collapsed */
if (a6xx_has_gbif(adreno_gpu))
if (a6xx_has_gbif(adreno_gpu)) {
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);
/* Let's make extra sure that the GPU can access the memory.. */
mb();
}
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);