platform/x86/intel/ifs: ARRAY BIST for Sierra Forest
Array BIST MSR addresses, bit definition and semantics are different for Sierra Forest. Branch into a separate Array BIST flow on Sierra Forest when user invokes Array Test. Signed-off-by: Jithu Joseph <jithu.joseph@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Tested-by: Pengfei Xu <pengfei.xu@intel.com> Link: https://lore.kernel.org/r/20231005195137.3117166-10-jithu.joseph@intel.com [ij: ARRAY_GEN_* -> ARRAY_GEN* for consistency] Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
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@ -11,16 +11,16 @@
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#include "ifs.h"
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#define X86_MATCH(model) \
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#define X86_MATCH(model, array_gen) \
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X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \
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INTEL_FAM6_##model, X86_FEATURE_CORE_CAPABILITIES, NULL)
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INTEL_FAM6_##model, X86_FEATURE_CORE_CAPABILITIES, array_gen)
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static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
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X86_MATCH(SAPPHIRERAPIDS_X),
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X86_MATCH(EMERALDRAPIDS_X),
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X86_MATCH(GRANITERAPIDS_X),
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X86_MATCH(GRANITERAPIDS_D),
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X86_MATCH(ATOM_CRESTMONT_X),
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X86_MATCH(SAPPHIRERAPIDS_X, ARRAY_GEN0),
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X86_MATCH(EMERALDRAPIDS_X, ARRAY_GEN0),
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X86_MATCH(GRANITERAPIDS_X, ARRAY_GEN0),
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X86_MATCH(GRANITERAPIDS_D, ARRAY_GEN0),
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X86_MATCH(ATOM_CRESTMONT_X, ARRAY_GEN1),
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{}
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};
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MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
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@ -100,6 +100,7 @@ static int __init ifs_init(void)
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continue;
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ifs_devices[i].rw_data.generation = FIELD_GET(MSR_INTEGRITY_CAPS_SAF_GEN_MASK,
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msrval);
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ifs_devices[i].rw_data.array_gen = (u32)m->driver_data;
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ret = misc_register(&ifs_devices[i].misc);
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if (ret)
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goto err_exit;
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@ -137,6 +137,8 @@
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#define MSR_CHUNKS_AUTHENTICATION_STATUS 0x000002c5
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#define MSR_ACTIVATE_SCAN 0x000002c6
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#define MSR_SCAN_STATUS 0x000002c7
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#define MSR_ARRAY_TRIGGER 0x000002d6
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#define MSR_ARRAY_STATUS 0x000002d7
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#define MSR_SAF_CTRL 0x000004f0
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#define SCAN_NOT_TESTED 0
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@ -146,6 +148,9 @@
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#define IFS_TYPE_SAF 0
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#define IFS_TYPE_ARRAY_BIST 1
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#define ARRAY_GEN0 0
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#define ARRAY_GEN1 1
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/* MSR_SCAN_HASHES_STATUS bit fields */
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union ifs_scan_hashes_status {
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u64 data;
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@ -272,6 +277,7 @@ struct ifs_test_caps {
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* @cur_batch: number indicating the currently loaded test file
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* @generation: IFS test generation enumerated by hardware
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* @chunk_size: size of a test chunk
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* @array_gen: test generation of array test
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*/
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struct ifs_data {
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int loaded_version;
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@ -283,6 +289,7 @@ struct ifs_data {
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u32 cur_batch;
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u32 generation;
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u32 chunk_size;
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u32 array_gen;
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};
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struct ifs_work {
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@ -329,6 +329,38 @@ static void ifs_array_test_core(int cpu, struct device *dev)
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ifsd->status = SCAN_TEST_PASS;
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}
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#define ARRAY_GEN1_TEST_ALL_ARRAYS 0x0ULL
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#define ARRAY_GEN1_STATUS_FAIL 0x1ULL
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static int do_array_test_gen1(void *status)
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{
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int cpu = smp_processor_id();
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int first;
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first = cpumask_first(cpu_smt_mask(cpu));
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if (cpu == first) {
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wrmsrl(MSR_ARRAY_TRIGGER, ARRAY_GEN1_TEST_ALL_ARRAYS);
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rdmsrl(MSR_ARRAY_STATUS, *((u64 *)status));
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}
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return 0;
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}
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static void ifs_array_test_gen1(int cpu, struct device *dev)
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{
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struct ifs_data *ifsd = ifs_get_data(dev);
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u64 status = 0;
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stop_core_cpuslocked(cpu, do_array_test_gen1, &status);
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ifsd->scan_details = status;
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if (status & ARRAY_GEN1_STATUS_FAIL)
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ifsd->status = SCAN_TEST_FAIL;
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else
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ifsd->status = SCAN_TEST_PASS;
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}
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/*
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* Initiate per core test. It wakes up work queue threads on the target cpu and
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* its sibling cpu. Once all sibling threads wake up, the scan test gets executed and
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@ -356,7 +388,10 @@ int do_core_test(int cpu, struct device *dev)
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ifs_test_core(cpu, dev);
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break;
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case IFS_TYPE_ARRAY_BIST:
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ifs_array_test_core(cpu, dev);
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if (ifsd->array_gen == ARRAY_GEN0)
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ifs_array_test_core(cpu, dev);
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else
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ifs_array_test_gen1(cpu, dev);
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break;
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default:
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return -EINVAL;
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