arm64: Move post_ttbr_update_workaround to C code
From: Marc Zyngier <marc.zyngier@arm.com> commit 95e3de3590e3f2358bb13f013911bc1bfa5d3f53 upstream. We will soon need to invoke a CPU-specific function pointer after changing page tables, so move post_ttbr_update_workaround out into C code to make this possible. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> [v4.9 backport] Tested-by: Greg Hackmann <ghackmann@google.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -435,17 +435,4 @@ alternative_endif
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and \phys, \pte, #(((1 << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
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.endm
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/*
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* Errata workaround post TTBR0_EL1 update.
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*/
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.macro post_ttbr0_update_workaround
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#ifdef CONFIG_CAVIUM_ERRATUM_27456
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alternative_if ARM64_WORKAROUND_CAVIUM_27456
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ic iallu
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dsb nsh
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isb
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alternative_else_nop_endif
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#endif
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.endm
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#endif /* __ASM_ASSEMBLER_H */
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@ -233,6 +233,15 @@ switch_mm_fastpath:
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cpu_switch_mm(mm->pgd, mm);
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}
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/* Errata workaround post TTBRx_EL1 update. */
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asmlinkage void post_ttbr_update_workaround(void)
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{
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asm(ALTERNATIVE("nop; nop; nop",
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"ic iallu; dsb nsh; isb",
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ARM64_WORKAROUND_CAVIUM_27456,
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CONFIG_CAVIUM_ERRATUM_27456));
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}
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static int asids_init(void)
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{
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asid_bits = get_cpu_asid_bits();
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@ -139,8 +139,7 @@ ENTRY(cpu_do_switch_mm)
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isb
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msr ttbr0_el1, x0 // now update TTBR0
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isb
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post_ttbr0_update_workaround
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ret
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b post_ttbr_update_workaround // Back to C code...
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ENDPROC(cpu_do_switch_mm)
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.pushsection ".idmap.text", "awx"
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