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Merge branch 'remotes/lorenzo/pci/bridge-emul'

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- Make emulated ROM BAR read-only by default (Pali Rohár)

- Make some emulated legacy PCI bits read-only for PCIe devices (Pali
  Rohár)

- Update reserved bits in emulated PCIe Capability (Pali Rohár)

- Allow drivers to emulate different PCIe Capability versions (Pali Rohár)

- Set emulated Capabilities List bit for all PCIe devices, since they must
  have at least a PCIe Capability (Pali Rohár)

* remotes/lorenzo/pci/bridge-emul:
  PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device
  PCI: pci-bridge-emul: Correctly set PCIe capabilities
  PCI: pci-bridge-emul: Fix definitions of reserved bits
  PCI: pci-bridge-emul: Properly mark reserved PCIe bits in PCI config space
  PCI: pci-bridge-emul: Make expansion ROM Base Address register read-only
This commit is contained in:
Bjorn Helgaas 2022-01-13 09:57:51 -06:00
commit 2709f0338d
3 changed files with 65 additions and 17 deletions
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4
drivers/pci/controller/pci-aardvark.c
View File

@ -883,7 +883,6 @@ advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
return PCI_BRIDGE_EMUL_HANDLED;
}
case PCI_CAP_LIST_ID:
case PCI_EXP_DEVCAP:
case PCI_EXP_DEVCTL:
case PCI_EXP_DEVCAP2:
@ -971,6 +970,9 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie)
/* Support interrupt A for MSI feature */
bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
/* Aardvark HW provides PCIe Capability structure in version 2 */
bridge->pcie_conf.cap = cpu_to_le16(2);
/* Indicates supports for Completion Retry Status */
bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS);

8
drivers/pci/controller/pci-mvebu.c
View File

@ -723,6 +723,8 @@ static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
{
struct pci_bridge_emul *bridge = &port->bridge;
u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP);
u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS);
bridge->conf.vendor = PCI_VENDOR_ID_MARVELL;
bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
@ -735,6 +737,12 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
}
/*
* Older mvebu hardware provides PCIe Capability structure only in
* version 1. New hardware provides it in version 2.
*/
bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver);
bridge->has_pcie = true;
bridge->data = port;
bridge->ops = &mvebu_pci_bridge_emul_ops;

70
drivers/pci/pci-bridge-emul.c
View File

@ -139,8 +139,13 @@ struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
.ro = GENMASK(7, 0),
},
/*
* If expansion ROM is unsupported then ROM Base Address register must
* be implemented as read-only register that return 0 when read, same
* as for unused Base Address registers.
*/
[PCI_ROM_ADDRESS1 / 4] = {
.rw = GENMASK(31, 11) | BIT(0),
.ro = ~0,
},
/*
@ -171,41 +176,55 @@ struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] =
[PCI_CAP_LIST_ID / 4] = {
/*
* Capability ID, Next Capability Pointer and
* Capabilities register are all read-only.
* bits [14:0] of Capabilities register are all read-only.
* Bit 15 of Capabilities register is reserved.
*/
.ro = ~0,
.ro = GENMASK(30, 0),
},
[PCI_EXP_DEVCAP / 4] = {
.ro = ~0,
/*
* Bits [31:29] and [17:16] are reserved.
* Bits [27:18] are reserved for non-upstream ports.
* Bits 28 and [14:6] are reserved for non-endpoint devices.
* Other bits are read-only.
*/
.ro = BIT(15) | GENMASK(5, 0),
},
[PCI_EXP_DEVCTL / 4] = {
/* Device control register is RW */
.rw = GENMASK(15, 0),
/*
* Device control register is RW, except bit 15 which is
* reserved for non-endpoints or non-PCIe-to-PCI/X bridges.
*/
.rw = GENMASK(14, 0),
/*
* Device status register has bits 6 and [3:0] W1C, [5:4] RO,
* the rest is reserved
* the rest is reserved. Also bit 6 is reserved for non-upstream
* ports.
*/
.w1c = (BIT(6) | GENMASK(3, 0)) << 16,
.w1c = GENMASK(3, 0) << 16,
.ro = GENMASK(5, 4) << 16,
},
[PCI_EXP_LNKCAP / 4] = {
/* All bits are RO, except bit 23 which is reserved */
.ro = lower_32_bits(~BIT(23)),
/*
* All bits are RO, except bit 23 which is reserved and
* bit 18 which is reserved for non-upstream ports.
*/
.ro = lower_32_bits(~(BIT(23) | PCI_EXP_LNKCAP_CLKPM)),
},
[PCI_EXP_LNKCTL / 4] = {
/*
* Link control has bits [15:14], [11:3] and [1:0] RW, the
* rest is reserved.
* rest is reserved. Bit 8 is reserved for non-upstream ports.
*
* Link status has bits [13:0] RO, and bits [15:14]
* W1C.
*/
.rw = GENMASK(15, 14) | GENMASK(11, 3) | GENMASK(1, 0),
.rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0),
.ro = GENMASK(13, 0) << 16,
.w1c = GENMASK(15, 14) << 16,
},
@ -324,11 +343,9 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
if (bridge->has_pcie) {
bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);
bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
/* Set PCIe v2, root port, slot support */
bridge->pcie_conf.cap =
cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
PCI_EXP_FLAGS_SLOT);
bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
bridge->pcie_cap_regs_behavior =
kmemdup(pcie_cap_regs_behavior,
sizeof(pcie_cap_regs_behavior),
@ -337,6 +354,27 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
kfree(bridge->pci_regs_behavior);
return -ENOMEM;
}
/* These bits are applicable only for PCI and reserved on PCIe */
bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
~GENMASK(15, 8);
bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
PCI_COMMAND_FAST_BACK) |
(PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
PCI_STATUS_DEVSEL_MASK) << 16);
bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
~GENMASK(31, 24);
bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
PCI_STATUS_DEVSEL_MASK) << 16);
bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
~((PCI_BRIDGE_CTL_MASTER_ABORT |
BIT(8) | BIT(9) | BIT(11)) << 16);
bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
~((PCI_BRIDGE_CTL_FAST_BACK) << 16);
bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
~(BIT(10) << 16);
}
if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) {