- Fix page fault issue at Mixer device
. This patch fixes the page fault issue by correcting sychronization method for updating shadow registers for Mixer device. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJck17SAAoJEFc4NIkMQxK4VHkP/jYOO+ByvOw1rlC1F1CfvYfT hQTa/pxrCtqUquLGUst+dc7bj8jTszlam5V3SpxRrlCWCiS3qrXuyzaWw6XnX9MT dcrha5TmxYXVHX7q3ISkI65qiav/drt1mHDfoRP8W7cOUrgssARfKi2xsyB+STnt 0JqfWD4WMZGcr8gx1b/Xjm6dqJQc3s4QB181lw5v5RkdpNbM2kVAYQ9dZ9iTBmFH QhyDJ4qJ3huqq9dG59RpQvr2AT/EmklFCfOuXqoJYV1cklR8qUFT4FZEqyN8KQsE cD2xX8FStZKlLWKKhexljGteLodRIF09hfc3Zwj9w3HPdEbtQwpMKWzjaGJ6DpXi fm3YkW8fYigY/pOUSwl5f25WP2QnhoZxU5olvSdAyaJPr2ajKxpCnZOT0lbQApOX Qseb3vX/rh2CUYBHndP0jXv+A8wdNWqNVR9sDAC3ENNfbxs4G8C2Mlp/L9MF/BRb nHxGvAsQG5ws5g+WNPFbAhD2ChWF4PYYUN+vSCUN/Pmz/LZBhdiDospE596KkTZV vURrZAoHSFJvYEe9FHUZeHhNWExhMm+TkEjkPj3xG4+Chc/L87Radycndy1wj804 ewMe+UHpyIDRQa/ql+XQaj6t/D6qm10FugHeWvmK6vgdWyQ19hEBYX/uKU2DlhtI SB4NWkrgchshZ3HPPFnW =5NcR -----END PGP SIGNATURE----- Merge tag 'exynos-drm-fixes-for-5.1-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-fixes - Fix page fault issue at Mixer device . This patch fixes the page fault issue by correcting sychronization method for updating shadow registers for Mixer device. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Inki Dae <inki.dae@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/1553162223-10090-1-git-send-email-inki.dae@samsung.com
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28d3ba6c99
@ -20,6 +20,7 @@
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#include "regs-vp.h"
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#include <linux/kernel.h>
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#include <linux/ktime.h>
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#include <linux/spinlock.h>
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#include <linux/wait.h>
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#include <linux/i2c.h>
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@ -352,15 +353,62 @@ static void mixer_cfg_vp_blend(struct mixer_context *ctx, unsigned int alpha)
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mixer_reg_write(ctx, MXR_VIDEO_CFG, val);
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}
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static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
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static bool mixer_is_synced(struct mixer_context *ctx)
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{
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/* block update on vsync */
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mixer_reg_writemask(ctx, MXR_STATUS, enable ?
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MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
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u32 base, shadow;
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if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
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ctx->mxr_ver == MXR_VER_128_0_0_184)
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return !(mixer_reg_read(ctx, MXR_CFG) &
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MXR_CFG_LAYER_UPDATE_COUNT_MASK);
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if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags) &&
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vp_reg_read(ctx, VP_SHADOW_UPDATE))
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return false;
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base = mixer_reg_read(ctx, MXR_CFG);
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shadow = mixer_reg_read(ctx, MXR_CFG_S);
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if (base != shadow)
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return false;
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base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0));
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shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0));
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if (base != shadow)
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return false;
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base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(1));
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shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(1));
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if (base != shadow)
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return false;
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return true;
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}
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static int mixer_wait_for_sync(struct mixer_context *ctx)
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{
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ktime_t timeout = ktime_add_us(ktime_get(), 100000);
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while (!mixer_is_synced(ctx)) {
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usleep_range(1000, 2000);
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if (ktime_compare(ktime_get(), timeout) > 0)
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void mixer_disable_sync(struct mixer_context *ctx)
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{
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mixer_reg_writemask(ctx, MXR_STATUS, 0, MXR_STATUS_SYNC_ENABLE);
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}
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static void mixer_enable_sync(struct mixer_context *ctx)
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{
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if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
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ctx->mxr_ver == MXR_VER_128_0_0_184)
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mixer_reg_writemask(ctx, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
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mixer_reg_writemask(ctx, MXR_STATUS, ~0, MXR_STATUS_SYNC_ENABLE);
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if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags))
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vp_reg_write(ctx, VP_SHADOW_UPDATE, enable ?
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VP_SHADOW_UPDATE_ENABLE : 0);
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vp_reg_write(ctx, VP_SHADOW_UPDATE, VP_SHADOW_UPDATE_ENABLE);
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}
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static void mixer_cfg_scan(struct mixer_context *ctx, int width, int height)
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@ -498,7 +546,6 @@ static void vp_video_buffer(struct mixer_context *ctx,
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spin_lock_irqsave(&ctx->reg_slock, flags);
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vp_reg_write(ctx, VP_SHADOW_UPDATE, 1);
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/* interlace or progressive scan mode */
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val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0);
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vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP);
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@ -553,11 +600,6 @@ static void vp_video_buffer(struct mixer_context *ctx,
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vp_regs_dump(ctx);
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}
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static void mixer_layer_update(struct mixer_context *ctx)
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{
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mixer_reg_writemask(ctx, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
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}
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static void mixer_graph_buffer(struct mixer_context *ctx,
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struct exynos_drm_plane *plane)
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{
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@ -640,11 +682,6 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
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mixer_cfg_layer(ctx, win, priority, true);
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mixer_cfg_gfx_blend(ctx, win, pixel_alpha, state->base.alpha);
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/* layer update mandatory for mixer 16.0.33.0 */
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if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
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ctx->mxr_ver == MXR_VER_128_0_0_184)
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mixer_layer_update(ctx);
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spin_unlock_irqrestore(&ctx->reg_slock, flags);
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mixer_regs_dump(ctx);
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@ -709,7 +746,7 @@ static void mixer_win_reset(struct mixer_context *ctx)
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static irqreturn_t mixer_irq_handler(int irq, void *arg)
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{
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struct mixer_context *ctx = arg;
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u32 val, base, shadow;
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u32 val;
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spin_lock(&ctx->reg_slock);
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@ -723,26 +760,9 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
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val &= ~MXR_INT_STATUS_VSYNC;
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/* interlace scan need to check shadow register */
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if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
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if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags) &&
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vp_reg_read(ctx, VP_SHADOW_UPDATE))
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goto out;
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base = mixer_reg_read(ctx, MXR_CFG);
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shadow = mixer_reg_read(ctx, MXR_CFG_S);
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if (base != shadow)
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goto out;
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base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0));
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shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0));
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if (base != shadow)
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goto out;
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base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(1));
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shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(1));
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if (base != shadow)
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goto out;
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}
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if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)
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&& !mixer_is_synced(ctx))
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goto out;
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drm_crtc_handle_vblank(&ctx->crtc->base);
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}
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@ -917,12 +937,14 @@ static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
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static void mixer_atomic_begin(struct exynos_drm_crtc *crtc)
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{
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struct mixer_context *mixer_ctx = crtc->ctx;
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struct mixer_context *ctx = crtc->ctx;
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if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
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if (!test_bit(MXR_BIT_POWERED, &ctx->flags))
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return;
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mixer_vsync_set_update(mixer_ctx, false);
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if (mixer_wait_for_sync(ctx))
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dev_err(ctx->dev, "timeout waiting for VSYNC\n");
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mixer_disable_sync(ctx);
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}
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static void mixer_update_plane(struct exynos_drm_crtc *crtc,
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@ -964,7 +986,7 @@ static void mixer_atomic_flush(struct exynos_drm_crtc *crtc)
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if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
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return;
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mixer_vsync_set_update(mixer_ctx, true);
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mixer_enable_sync(mixer_ctx);
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exynos_crtc_handle_event(crtc);
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}
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@ -979,7 +1001,7 @@ static void mixer_enable(struct exynos_drm_crtc *crtc)
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exynos_drm_pipe_clk_enable(crtc, true);
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mixer_vsync_set_update(ctx, false);
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mixer_disable_sync(ctx);
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mixer_reg_writemask(ctx, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
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@ -992,7 +1014,7 @@ static void mixer_enable(struct exynos_drm_crtc *crtc)
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mixer_commit(ctx);
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mixer_vsync_set_update(ctx, true);
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mixer_enable_sync(ctx);
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set_bit(MXR_BIT_POWERED, &ctx->flags);
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}
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