Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
Pull sparc updates from David Miller: "Just a couple of fixes/cleanups: - Correct NUMA latency calculations on sparc64, from Nitin Gupta. - ASI_ST_BLKINIT_MRU_S value was wrong, from Rob Gardner. - Fix non-faulting load handling of non-quad values, also from Rob Gardner. - Cleanup VISsave assembler, from Sam Ravnborg. - Fix iommu-common code so it doesn't emit rediculous warnings on some architectures, particularly ARM" * git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc: sparc64: Fix numa distance values sparc64: Don't restrict fp regs for no-fault loads iommu-common: Fix error code used in iommu_tbl_range_{alloc,free}(). sparc64: use ENTRY/ENDPROC in VISsave sparc64: Fix incorrect ASI_ST_BLKINIT_MRU_S value
This commit is contained in:
commit
2c302e7e41
@ -31,6 +31,9 @@ static inline int pcibus_to_node(struct pci_bus *pbus)
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cpu_all_mask : \
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cpumask_of_node(pcibus_to_node(bus)))
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int __node_distance(int, int);
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#define node_distance(a, b) __node_distance(a, b)
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#else /* CONFIG_NUMA */
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#include <asm-generic/topology.h>
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@ -279,7 +279,7 @@
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* Most-Recently-Used, primary,
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* implicit
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*/
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#define ASI_ST_BLKINIT_MRU_S 0xf2 /* (NG4) init-store, twin load,
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#define ASI_ST_BLKINIT_MRU_S 0xf3 /* (NG4) init-store, twin load,
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* Most-Recently-Used, secondary,
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* implicit
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*/
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@ -161,7 +161,7 @@ static inline iopte_t *alloc_npages(struct device *dev,
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entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
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(unsigned long)(-1), 0);
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if (unlikely(entry == DMA_ERROR_CODE))
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if (unlikely(entry == IOMMU_ERROR_CODE))
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return NULL;
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return iommu->page_table + entry;
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@ -253,7 +253,7 @@ static void dma_4u_free_coherent(struct device *dev, size_t size,
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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iommu = dev->archdata.iommu;
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iommu_tbl_range_free(&iommu->tbl, dvma, npages, DMA_ERROR_CODE);
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iommu_tbl_range_free(&iommu->tbl, dvma, npages, IOMMU_ERROR_CODE);
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order = get_order(size);
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if (order < 10)
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@ -426,7 +426,7 @@ static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr,
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iommu_free_ctx(iommu, ctx);
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spin_unlock_irqrestore(&iommu->lock, flags);
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iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, DMA_ERROR_CODE);
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iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, IOMMU_ERROR_CODE);
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}
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static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
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@ -492,7 +492,7 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
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&handle, (unsigned long)(-1), 0);
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/* Handle failure */
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if (unlikely(entry == DMA_ERROR_CODE)) {
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if (unlikely(entry == IOMMU_ERROR_CODE)) {
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if (printk_ratelimit())
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printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
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" npages %lx\n", iommu, paddr, npages);
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@ -571,7 +571,7 @@ iommu_map_failed:
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iopte_make_dummy(iommu, base + j);
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iommu_tbl_range_free(&iommu->tbl, vaddr, npages,
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DMA_ERROR_CODE);
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IOMMU_ERROR_CODE);
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s->dma_address = DMA_ERROR_CODE;
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s->dma_length = 0;
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@ -648,7 +648,7 @@ static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
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iopte_make_dummy(iommu, base + i);
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iommu_tbl_range_free(&iommu->tbl, dma_handle, npages,
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DMA_ERROR_CODE);
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IOMMU_ERROR_CODE);
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sg = sg_next(sg);
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}
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@ -1953,7 +1953,7 @@ static struct ldc_mtable_entry *alloc_npages(struct ldc_iommu *iommu,
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entry = iommu_tbl_range_alloc(NULL, &iommu->iommu_map_table,
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npages, NULL, (unsigned long)-1, 0);
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if (unlikely(entry < 0))
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if (unlikely(entry == IOMMU_ERROR_CODE))
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return NULL;
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return iommu->page_table + entry;
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@ -159,7 +159,7 @@ static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
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entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
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(unsigned long)(-1), 0);
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if (unlikely(entry == DMA_ERROR_CODE))
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if (unlikely(entry == IOMMU_ERROR_CODE))
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goto range_alloc_fail;
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*dma_addrp = (iommu->tbl.table_map_base + (entry << IO_PAGE_SHIFT));
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@ -187,7 +187,7 @@ static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
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return ret;
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iommu_map_fail:
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iommu_tbl_range_free(&iommu->tbl, *dma_addrp, npages, DMA_ERROR_CODE);
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iommu_tbl_range_free(&iommu->tbl, *dma_addrp, npages, IOMMU_ERROR_CODE);
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range_alloc_fail:
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free_pages(first_page, order);
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@ -226,7 +226,7 @@ static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
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devhandle = pbm->devhandle;
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entry = ((dvma - iommu->tbl.table_map_base) >> IO_PAGE_SHIFT);
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dma_4v_iommu_demap(&devhandle, entry, npages);
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iommu_tbl_range_free(&iommu->tbl, dvma, npages, DMA_ERROR_CODE);
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iommu_tbl_range_free(&iommu->tbl, dvma, npages, IOMMU_ERROR_CODE);
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order = get_order(size);
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if (order < 10)
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free_pages((unsigned long)cpu, order);
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@ -256,7 +256,7 @@ static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
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entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
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(unsigned long)(-1), 0);
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if (unlikely(entry == DMA_ERROR_CODE))
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if (unlikely(entry == IOMMU_ERROR_CODE))
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goto bad;
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bus_addr = (iommu->tbl.table_map_base + (entry << IO_PAGE_SHIFT));
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@ -288,7 +288,7 @@ bad:
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return DMA_ERROR_CODE;
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iommu_map_fail:
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iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, DMA_ERROR_CODE);
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iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, IOMMU_ERROR_CODE);
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return DMA_ERROR_CODE;
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}
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@ -317,7 +317,7 @@ static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
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bus_addr &= IO_PAGE_MASK;
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entry = (bus_addr - iommu->tbl.table_map_base) >> IO_PAGE_SHIFT;
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dma_4v_iommu_demap(&devhandle, entry, npages);
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iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, DMA_ERROR_CODE);
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iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, IOMMU_ERROR_CODE);
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}
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static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
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@ -376,7 +376,7 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
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&handle, (unsigned long)(-1), 0);
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/* Handle failure */
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if (unlikely(entry == DMA_ERROR_CODE)) {
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if (unlikely(entry == IOMMU_ERROR_CODE)) {
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if (printk_ratelimit())
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printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
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" npages %lx\n", iommu, paddr, npages);
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@ -451,7 +451,7 @@ iommu_map_failed:
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npages = iommu_num_pages(s->dma_address, s->dma_length,
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IO_PAGE_SIZE);
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iommu_tbl_range_free(&iommu->tbl, vaddr, npages,
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DMA_ERROR_CODE);
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IOMMU_ERROR_CODE);
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/* XXX demap? XXX */
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s->dma_address = DMA_ERROR_CODE;
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s->dma_length = 0;
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@ -496,7 +496,7 @@ static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
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entry = ((dma_handle - tbl->table_map_base) >> shift);
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dma_4v_iommu_demap(&devhandle, entry, npages);
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iommu_tbl_range_free(&iommu->tbl, dma_handle, npages,
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DMA_ERROR_CODE);
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IOMMU_ERROR_CODE);
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sg = sg_next(sg);
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}
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@ -436,24 +436,26 @@ extern void sun4v_data_access_exception(struct pt_regs *regs,
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int handle_ldf_stq(u32 insn, struct pt_regs *regs)
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{
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unsigned long addr = compute_effective_address(regs, insn, 0);
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int freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
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int freg;
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struct fpustate *f = FPUSTATE;
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int asi = decode_asi(insn, regs);
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int flag = (freg < 32) ? FPRS_DL : FPRS_DU;
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int flag;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
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save_and_clear_fpu();
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current_thread_info()->xfsr[0] &= ~0x1c000;
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if (freg & 3) {
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current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
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do_fpother(regs);
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return 0;
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}
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if (insn & 0x200000) {
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/* STQ */
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u64 first = 0, second = 0;
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freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
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flag = (freg < 32) ? FPRS_DL : FPRS_DU;
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if (freg & 3) {
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current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
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do_fpother(regs);
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return 0;
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}
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if (current_thread_info()->fpsaved[0] & flag) {
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first = *(u64 *)&f->regs[freg];
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second = *(u64 *)&f->regs[freg+2];
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@ -513,6 +515,12 @@ int handle_ldf_stq(u32 insn, struct pt_regs *regs)
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case 0x100000: size = 4; break;
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default: size = 2; break;
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}
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if (size == 1)
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freg = (insn >> 25) & 0x1f;
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else
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freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
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flag = (freg < 32) ? FPRS_DL : FPRS_DU;
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for (i = 0; i < size; i++)
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data[i] = 0;
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@ -6,24 +6,23 @@
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <linux/linkage.h>
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#include <asm/asi.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include <asm/visasm.h>
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#include <asm/thread_info.h>
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.text
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.globl VISenter, VISenterhalf
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/* On entry: %o5=current FPRS value, %g7 is callers address */
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/* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
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/* Nothing special need be done here to handle pre-emption, this
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* FPU save/restore mechanism is already preemption safe.
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*/
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.text
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.align 32
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VISenter:
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ENTRY(VISenter)
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ldub [%g6 + TI_FPDEPTH], %g1
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brnz,a,pn %g1, 1f
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cmp %g1, 1
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@ -79,3 +78,4 @@ vis1: ldub [%g6 + TI_FPSAVED], %g3
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.align 32
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80: jmpl %g7 + %g0, %g0
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nop
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ENDPROC(VISenter)
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@ -93,6 +93,8 @@ static unsigned long cpu_pgsz_mask;
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static struct linux_prom64_registers pavail[MAX_BANKS];
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static int pavail_ents;
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u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
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static int cmp_p64(const void *a, const void *b)
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{
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const struct linux_prom64_registers *x = a, *y = b;
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@ -1157,6 +1159,48 @@ static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
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return NULL;
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}
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int __node_distance(int from, int to)
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{
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if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
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pr_warn("Returning default NUMA distance value for %d->%d\n",
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from, to);
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return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
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}
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return numa_latency[from][to];
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}
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static int find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
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{
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int i;
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for (i = 0; i < MAX_NUMNODES; i++) {
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struct node_mem_mask *n = &node_masks[i];
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if ((grp->mask == n->mask) && (grp->match == n->val))
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break;
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}
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return i;
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}
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static void find_numa_latencies_for_group(struct mdesc_handle *md, u64 grp,
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int index)
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{
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u64 arc;
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mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
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int tnode;
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u64 target = mdesc_arc_target(md, arc);
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struct mdesc_mlgroup *m = find_mlgroup(target);
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if (!m)
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continue;
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tnode = find_best_numa_node_for_mlgroup(m);
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if (tnode == MAX_NUMNODES)
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continue;
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numa_latency[index][tnode] = m->latency;
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}
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}
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static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
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int index)
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{
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@ -1220,9 +1264,16 @@ static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
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static int __init numa_parse_mdesc(void)
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{
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struct mdesc_handle *md = mdesc_grab();
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int i, err, count;
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int i, j, err, count;
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u64 node;
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/* Some sane defaults for numa latency values */
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for (i = 0; i < MAX_NUMNODES; i++) {
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for (j = 0; j < MAX_NUMNODES; j++)
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numa_latency[i][j] = (i == j) ?
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LOCAL_DISTANCE : REMOTE_DISTANCE;
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}
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node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
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if (node == MDESC_NODE_NULL) {
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mdesc_release(md);
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@ -1245,6 +1296,23 @@ static int __init numa_parse_mdesc(void)
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count++;
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}
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count = 0;
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mdesc_for_each_node_by_name(md, node, "group") {
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find_numa_latencies_for_group(md, node, count);
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count++;
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}
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/* Normalize numa latency matrix according to ACPI SLIT spec. */
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for (i = 0; i < MAX_NUMNODES; i++) {
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u64 self_latency = numa_latency[i][i];
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for (j = 0; j < MAX_NUMNODES; j++) {
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numa_latency[i][j] =
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(numa_latency[i][j] * LOCAL_DISTANCE) /
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self_latency;
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}
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}
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add_node_ranges();
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for (i = 0; i < num_node_masks; i++) {
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|
@ -7,6 +7,7 @@
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#define IOMMU_POOL_HASHBITS 4
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#define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS)
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#define IOMMU_ERROR_CODE (~(unsigned long) 0)
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struct iommu_pool {
|
||||
unsigned long start;
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|
@ -11,10 +11,6 @@
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#include <linux/dma-mapping.h>
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#include <linux/hash.h>
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||||
#ifndef DMA_ERROR_CODE
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#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
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#endif
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||||
static unsigned long iommu_large_alloc = 15;
|
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||||
static DEFINE_PER_CPU(unsigned int, iommu_hash_common);
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@ -123,7 +119,7 @@ unsigned long iommu_tbl_range_alloc(struct device *dev,
|
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/* Sanity check */
|
||||
if (unlikely(npages == 0)) {
|
||||
WARN_ON_ONCE(1);
|
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return DMA_ERROR_CODE;
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||||
return IOMMU_ERROR_CODE;
|
||||
}
|
||||
|
||||
if (largealloc) {
|
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@ -206,7 +202,7 @@ unsigned long iommu_tbl_range_alloc(struct device *dev,
|
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goto again;
|
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} else {
|
||||
/* give up */
|
||||
n = DMA_ERROR_CODE;
|
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n = IOMMU_ERROR_CODE;
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goto bail;
|
||||
}
|
||||
}
|
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@ -259,7 +255,7 @@ void iommu_tbl_range_free(struct iommu_map_table *iommu, u64 dma_addr,
|
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unsigned long flags;
|
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unsigned long shift = iommu->table_shift;
|
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|
||||
if (entry == DMA_ERROR_CODE) /* use default addr->entry mapping */
|
||||
if (entry == IOMMU_ERROR_CODE) /* use default addr->entry mapping */
|
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entry = (dma_addr - iommu->table_map_base) >> shift;
|
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pool = get_pool(iommu, entry);
|
||||
|
||||
|
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