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clk: lmk04832: Fix spelling mistakes in dev_err messages and comments

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There are handful of spelling mistakes in two dev_err error messages
and comments. Fix them.

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20210629102956.17901-1-colin.king@canonical.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Colin Ian King 2021-06-29 11:29:56 +01:00 committed by Stephen Boyd
parent b424f73b6c
commit 2cdee50eda
1 changed files with 4 additions and 4 deletions
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8
drivers/clk/clk-lmk04832.c
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@ -519,7 +519,7 @@ static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate,
vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r);
if (vco_rate < 0) {
dev_err(lmk->dev, "PLL2 parmeters out of range\n");
dev_err(lmk->dev, "PLL2 parameters out of range\n");
return vco_rate;
}
@ -550,7 +550,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);
if (vco_rate < 0) {
dev_err(lmk->dev, "failed to determine PLL2 parmeters\n");
dev_err(lmk->dev, "failed to determine PLL2 parameters\n");
return vco_rate;
}
@ -573,7 +573,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
/*
* PLL2_N registers must be programmed after other PLL2 dividers are
* programed to ensure proper VCO frequency calibration
* programmed to ensure proper VCO frequency calibration
*/
ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,
FIELD_GET(0x030000, n));
@ -1120,7 +1120,7 @@ static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
return -EINVAL;
}
/* Enable Duty Cycle Corretion */
/* Enable Duty Cycle Correction */
if (dclk_div == 1) {
ret = regmap_update_bits(lmk->regmap,
LMK04832_REG_CLKOUT_CTRL3(dclk->id),