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ARM: Xilinx Zynq SoC patches for v5.6

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- Fix cpuid handling logic in platform SMP startup code
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Merge tag 'zynq-soc-for-v5.6' of https://github.com/Xilinx/linux-xlnx into arm/soc

ARM: Xilinx Zynq SoC patches for v5.6

- Fix cpuid handling logic in platform SMP startup code

* tag 'zynq-soc-for-v5.6' of https://github.com/Xilinx/linux-xlnx:
  ARM: zynq: use physical cpuid in zynq_slcr_cpu_stop/start

Link: https://lore.kernel.org/r/50dec3cf-5f80-69be-c3d1-cc14b9bce5ff@monstr.eu
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2020-01-21 15:07:03 -08:00
commit 31a7d26fbc
1 changed files with 4 additions and 2 deletions
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6
arch/arm/mach-zynq/platsmp.c
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@ -15,6 +15,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"
@ -30,6 +31,7 @@ int zynq_cpun_start(u32 address, int cpu)
{
u32 trampoline_code_size = &zynq_secondary_trampoline_end -
&zynq_secondary_trampoline;
u32 phy_cpuid = cpu_logical_map(cpu);
/* MS: Expectation that SLCR are directly map and accessible */
/* Not possible to jump to non aligned address */
@ -39,7 +41,7 @@ int zynq_cpun_start(u32 address, int cpu)
u32 trampoline_size = &zynq_secondary_trampoline_jump -
&zynq_secondary_trampoline;
zynq_slcr_cpu_stop(cpu);
zynq_slcr_cpu_stop(phy_cpuid);
if (address) {
if (__pa(PAGE_OFFSET)) {
zero = ioremap(0, trampoline_code_size);
@ -68,7 +70,7 @@ int zynq_cpun_start(u32 address, int cpu)
if (__pa(PAGE_OFFSET))
iounmap(zero);
}
zynq_slcr_cpu_start(cpu);
zynq_slcr_cpu_start(phy_cpuid);
return 0;
}