ASoC: fsl_sai: Initialize with software reset
This patch adds software reset code in dai_probe() so as to make a true init by clearing SAI's internal logic, including the bit clock generation, status flags, and FIFO pointers. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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@ -437,8 +437,13 @@ static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
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{
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struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
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regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 0xffffffff, 0x0);
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regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 0xffffffff, 0x0);
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/* Software Reset for both Tx and Rx */
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regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
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regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
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/* Clear SR bit to finish the reset */
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regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
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regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
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regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
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FSL_SAI_MAXBURST_TX * 2);
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regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
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@ -48,6 +48,7 @@
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/* SAI Transmit/Recieve Control Register */
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#define FSL_SAI_CSR_TERE BIT(31)
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#define FSL_SAI_CSR_FR BIT(25)
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#define FSL_SAI_CSR_SR BIT(24)
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#define FSL_SAI_CSR_xF_SHIFT 16
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#define FSL_SAI_CSR_xF_W_SHIFT 18
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#define FSL_SAI_CSR_xF_MASK (0x1f << FSL_SAI_CSR_xF_SHIFT)
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