drm/amdgpu: update default timeout of Aldebaran SQ watchdog
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reivewed-by: Hawking Zhang <hawking.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -177,7 +177,7 @@ uint amdgpu_ras_mask = 0xffffffff;
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int amdgpu_bad_page_threshold = 100;
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struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
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.timeout_fatal_disable = false,
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.period = 0x3f, /* about 8s */
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.period = 0x23, /* default to max. timeout = 1 << 0x23 cycles */
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};
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/**
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@ -545,7 +545,7 @@ module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_di
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* DOC: timeout_period (uint)
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* Modify the watchdog timeout max_cycles as (1 << period)
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*/
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MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0x1F = default), timeout maxCycles = (1 << period)");
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MODULE_PARM_DESC(timeout_period, "watchdog timeout period (1 to 0x23(default), timeout maxCycles = (1 << period)");
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module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
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/**
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@ -1138,6 +1138,13 @@ void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev)
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data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
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amdgpu_watchdog_timer.timeout_fatal_disable ? 1 :
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0);
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if (amdgpu_watchdog_timer.timeout_fatal_disable &&
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(amdgpu_watchdog_timer.period < 1 ||
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amdgpu_watchdog_timer.period > 0x23)) {
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dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n");
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amdgpu_watchdog_timer.period = 0x23;
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}
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data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,
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amdgpu_watchdog_timer.period);
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