pwm: dwc: add PWM bit unset in get_state call
If we are not in PWM mode, then the output is technically a 50% output based on a single timer instead of the high-low based on the two counters. Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230907161242.67190-4-ben.dooks@codethink.co.uk Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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@ -122,24 +122,32 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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{
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struct dwc_pwm *dwc = to_dwc_pwm(chip);
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u64 duty, period;
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u32 ctrl, ld, ld2;
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pm_runtime_get_sync(chip->dev);
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state->enabled = !!(dwc_pwm_readl(dwc,
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DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN);
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ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm));
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ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
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ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
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duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
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duty += 1;
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duty *= dwc->clk_ns;
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state->duty_cycle = duty;
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state->enabled = !!(ctrl & DWC_TIM_CTRL_EN);
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period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
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period += 1;
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period *= dwc->clk_ns;
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period += duty;
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state->period = period;
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/*
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* If we're not in PWM, technically the output is a 50-50
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* based on the timer load-count only.
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*/
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if (ctrl & DWC_TIM_CTRL_PWM) {
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duty = (ld + 1) * dwc->clk_ns;
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period = (ld2 + 1) * dwc->clk_ns;
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period += duty;
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} else {
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duty = (ld + 1) * dwc->clk_ns;
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period = duty * 2;
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}
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state->polarity = PWM_POLARITY_INVERSED;
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state->period = period;
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state->duty_cycle = duty;
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pm_runtime_put_sync(chip->dev);
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