drm/i915: Pipe palette registers need an offset on VLV

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2013-01-24 15:29:47 +02:00 committed by Daniel Vetter
parent 4e8e7eb703
commit 4b0599854b

View File

@ -1166,8 +1166,8 @@
* Palette regs
*/
#define _PALETTE_A 0x0a000
#define _PALETTE_B 0x0a800
#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
/* MCH MMIO space */