drm/i915: Pipe palette registers need an offset on VLV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1166,8 +1166,8 @@
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* Palette regs
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*/
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#define _PALETTE_A 0x0a000
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#define _PALETTE_B 0x0a800
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#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
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#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
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#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
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/* MCH MMIO space */
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