drm/i915/hwmon: Expose power1_max_interval
Expose power1_max_interval, that is the tau corresponding to PL1, as a custom hwmon attribute. Some bit manipulation is needed because of the format of PKG_PWR_LIM_1_TIME in GT0_PACKAGE_RAPL_LIMIT register (1.x * power(2,y)). v2: Update date and kernel version in Documentation (Badal) v3: Cleaned up hwm_power1_max_interval_store() (Badal) v4: - Fixed review comments (Anshuman) - In hwm_power1_max_interval_store() get PKG_MAX_WIN from pkg_power_sku when it is valid (Ashutosh) - KernelVersion: 6.2, Date: February 2023 in doc (Tvrtko) v5: On some of the DGFX setups it is seen that although pkg_power_sku is valid the field PKG_WIN_MAX is not populated. So it is decided to stick to default value of PKG_WIN_MAX (Ashutosh) v6: Change contact to intel-gfx (Rodrigo) Fixed variable types in hwm_power1_max_interval_store (Andi) Documented PKG_MAX_WIN_DEFAULT (Andi) Removed else in hwm_attributes_visible (Andi) Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221013154526.2105579-7-ashutosh.dixit@intel.com
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@ -26,6 +26,15 @@ Description: RO. Card default power limit (default TDP setting).
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Only supported for particular Intel i915 graphics platforms.
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What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval
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Date: February 2023
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KernelVersion: 6.2
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Contact: intel-gfx@lists.freedesktop.org
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Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
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milliseconds over which sustained power is averaged.
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Only supported for particular Intel i915 graphics platforms.
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What: /sys/devices/.../hwmon/hwmon<i>/power1_crit
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Date: February 2023
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KernelVersion: 6.2
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@ -20,11 +20,13 @@
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* - power - microwatts
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* - curr - milliamperes
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* - energy - microjoules
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* - time - milliseconds
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*/
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#define SF_VOLTAGE 1000
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#define SF_POWER 1000000
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#define SF_CURR 1000
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#define SF_ENERGY 1000000
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#define SF_TIME 1000
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struct hwm_reg {
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i915_reg_t gt_perf_status;
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@ -53,6 +55,7 @@ struct i915_hwmon {
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struct hwm_reg rg;
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int scl_shift_power;
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int scl_shift_energy;
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int scl_shift_time;
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};
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static void
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@ -159,6 +162,119 @@ hwm_energy(struct hwm_drvdata *ddat, long *energy)
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mutex_unlock(&hwmon->hwmon_lock);
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}
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static ssize_t
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hwm_power1_max_interval_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct hwm_drvdata *ddat = dev_get_drvdata(dev);
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struct i915_hwmon *hwmon = ddat->hwmon;
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intel_wakeref_t wakeref;
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u32 r, x, y, x_w = 2; /* 2 bits */
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u64 tau4, out;
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with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
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r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit);
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x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
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y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
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/*
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* tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
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* = (4 | x) << (y - 2)
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* where (y - 2) ensures a 1.x fixed point representation of 1.x
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* However because y can be < 2, we compute
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* tau4 = (4 | x) << y
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* but add 2 when doing the final right shift to account for units
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*/
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tau4 = ((1 << x_w) | x) << y;
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/* val in hwmon interface units (millisec) */
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out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
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return sysfs_emit(buf, "%llu\n", out);
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}
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static ssize_t
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hwm_power1_max_interval_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct hwm_drvdata *ddat = dev_get_drvdata(dev);
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struct i915_hwmon *hwmon = ddat->hwmon;
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u32 x, y, rxy, x_w = 2; /* 2 bits */
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u64 tau4, r, max_win;
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unsigned long val;
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int ret;
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ret = kstrtoul(buf, 0, &val);
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if (ret)
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return ret;
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/*
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* Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12
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* The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds
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*/
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#define PKG_MAX_WIN_DEFAULT 0x12ull
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/*
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* val must be < max in hwmon interface units. The steps below are
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* explained in i915_power1_max_interval_show()
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*/
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r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
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x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
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y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
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tau4 = ((1 << x_w) | x) << y;
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max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
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if (val > max_win)
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return -EINVAL;
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/* val in hw units */
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val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
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/* Convert to 1.x * power(2,y) */
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if (!val)
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return -EINVAL;
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y = ilog2(val);
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/* x = (val - (1 << y)) >> (y - 2); */
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x = (val - (1ul << y)) << x_w >> y;
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rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
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hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit,
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PKG_PWR_LIM_1_TIME, rxy);
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return count;
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}
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static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
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hwm_power1_max_interval_show,
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hwm_power1_max_interval_store, 0);
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static struct attribute *hwm_attributes[] = {
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&sensor_dev_attr_power1_max_interval.dev_attr.attr,
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NULL
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};
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static umode_t hwm_attributes_visible(struct kobject *kobj,
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struct attribute *attr, int index)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct hwm_drvdata *ddat = dev_get_drvdata(dev);
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struct i915_hwmon *hwmon = ddat->hwmon;
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if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
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return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? attr->mode : 0;
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return 0;
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}
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static const struct attribute_group hwm_attrgroup = {
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.attrs = hwm_attributes,
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.is_visible = hwm_attributes_visible,
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};
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static const struct attribute_group *hwm_groups[] = {
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&hwm_attrgroup,
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NULL
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};
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static const struct hwmon_channel_info *hwm_info[] = {
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HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
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HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
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@ -471,6 +587,7 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
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hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
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hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
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hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
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/*
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* Initialize 'struct hwm_energy_info', i.e. set fields to the
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@ -509,7 +626,7 @@ void i915_hwmon_register(struct drm_i915_private *i915)
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hwmon_dev = devm_hwmon_device_register_with_info(dev, ddat->name,
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ddat,
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&hwm_chip_info,
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NULL);
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hwm_groups);
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if (IS_ERR(hwmon_dev)) {
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i915->hwmon = NULL;
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return;
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@ -194,6 +194,9 @@
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*/
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#define PCU_PACKAGE_POWER_SKU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5930)
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#define PKG_PKG_TDP GENMASK_ULL(14, 0)
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#define PKG_MAX_WIN GENMASK_ULL(54, 48)
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#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
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#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
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#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)
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#define PKG_PWR_UNIT REG_GENMASK(3, 0)
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@ -212,6 +215,10 @@
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#define RPE_MASK REG_GENMASK(15, 8)
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#define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
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#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
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#define PKG_PWR_LIM_1_EN REG_BIT(15)
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#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
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#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
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#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
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/* snb MCH registers for priority tuning */
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#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
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