* Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH)
* Add new compatible to the meson8 clock controller for meson8b * Add missing parents to gxbb clk81 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJZRDQVAAoJEAFRo5MEFpTRaVgQAKqGVc39PNOGuzx8P2pj4H0B lhedpQu7XHTGc7/2/b8ezMwzgnlHnFsAJOnzpLj4FbUNbNSlJmJFaBfybbV1cgd+ MF1cN9D5ssqI5zjkXeIhhZO6ogoe3AUlhjqKJMQfK2jlbQdF9Y9GrCIFFdzj/xC8 pwI4UxRg1g0SGfsF76IaGWeBsduYr9kzZJ3Xr1zUIi32bn/peTaHL+Ye/tv8ssir NPnIXDte8XV+gmlOk0Ir1ELqIt501UfbljKmknU4FtVmOH9B/xkuxxOZU0w0Ia1o 6uoXKDMVENQO+LFWifdexIKh5MV7fXC1wynYoiqTd0BiOA2vKryTo4lcqPblWA5T V95wIqwjsk6+XHl5uEFT7HPm2V5QEmBKzeDA4ng6hlGB7GYxZFhpzZQK4lnNrML0 pB+crpY9/5lAdQlpC/XMkOHORhJ0862ktT45TplToprowWadnmLZBbHB7QcNe+iH z8v26eoh800YTN5KMfiSjPXNRW6GPS8YKJmT/9vx35+ysKFMD2fW2FmM7DL5LN+M Bv+fgbJSJ4slniqMzFCEVWfcMESGltAYKM8G2YpPUF1uf99SnRweFwf7tshPSvJ4 bhvnqUdKsWxMgag3aL2D5eKq+yCRlk6/3zobq5qlCAomr9XDMm97C4CGmFUn40iV xiIzVBXoiydjJyaBLSzX =0BO9 -----END PGP SIGNATURE----- Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into clk-next Pull Amlogic clk driver updates from Jerome Brunet: * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH) * Add new compatible to the meson8 clock controller for meson8b * Add missing parents to gxbb clk81 * tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson: clk: meson: gxbb: add all clk81 parents clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 clk: meson8b: export the ethernet gate clock clk: meson8b: export the USB clocks clk: meson8b: export the gate clock for the HW random number generator clk: meson8b: export the SDIO clock clk: meson8b: export the SAR ADC clocks
This commit is contained in:
Stephen Boyd
commit
4dea04c1f1
@ -1,11 +1,14 @@
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* Amlogic Meson8b Clock and Reset Unit
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* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
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The Amlogic Meson8b clock controller generates and supplies clock to various
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controllers within the SoC.
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The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
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supplies clock to various controllers within the SoC.
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Required Properties:
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- compatible: should be "amlogic,meson8b-clkc"
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- compatible: must be one of:
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- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
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- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
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- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
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- reg: it must be composed by two tuples:
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0) physical base address of the xtal register and length of memory
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mapped region.
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@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B
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bool
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depends on COMMON_CLK_AMLOGIC
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help
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Support for the clock controller on AmLogic S805 devices, aka
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meson8b. Say Y if you want peripherals and CPU frequency scaling to
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work.
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Support for the clock controller on AmLogic S802 (Meson8),
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S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
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want peripherals and CPU frequency scaling to work.
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config COMMON_CLK_GXBB
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bool
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@ -603,7 +603,11 @@ static struct meson_clk_mpll gxbb_mpll2 = {
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* coordinated clock rates feature
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*/
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static u32 mux_table_clk81[] = { 6, 5, 7 };
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static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
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static const char * const clk81_parent_names[] = {
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"xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
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"fclk_div3", "fclk_div5"
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};
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static struct clk_mux gxbb_mpeg_clk_sel = {
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.reg = (void *)HHI_MPEG_CLK_CNTL,
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@ -616,13 +620,12 @@ static struct clk_mux gxbb_mpeg_clk_sel = {
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.name = "mpeg_clk_sel",
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.ops = &clk_mux_ro_ops,
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/*
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* FIXME bits 14:12 selects from 8 possible parents:
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* bits 14:12 selects from 8 possible parents:
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* xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
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* fclk_div4, fclk_div3, fclk_div5
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*/
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.parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
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"fclk_div5" },
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.num_parents = 3,
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.parent_names = clk81_parent_names,
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.num_parents = ARRAY_SIZE(clk81_parent_names),
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.flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
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},
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};
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@ -1,5 +1,6 @@
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/*
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* AmLogic S805 / Meson8b Clock Controller Driver
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* AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
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* Driver
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*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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@ -777,7 +778,9 @@ iounmap:
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}
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static const struct of_device_id meson8b_clkc_match_table[] = {
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{ .compatible = "amlogic,meson8-clkc" },
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{ .compatible = "amlogic,meson8b-clkc" },
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{ .compatible = "amlogic,meson8m2-clkc" },
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{ }
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};
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@ -87,20 +87,20 @@
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#define CLKID_PERIPHS 20
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#define CLKID_SPICC 21
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#define CLKID_I2C 22
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#define CLKID_SAR_ADC 23
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/* #define CLKID_SAR_ADC */
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#define CLKID_SMART_CARD 24
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#define CLKID_RNG0 25
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/* #define CLKID_RNG0 */
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#define CLKID_UART0 26
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#define CLKID_SDHC 27
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#define CLKID_STREAM 28
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#define CLKID_ASYNC_FIFO 29
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#define CLKID_SDIO 30
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/* #define CLKID_SDIO */
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#define CLKID_ABUF 31
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#define CLKID_HIU_IFACE 32
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#define CLKID_ASSIST_MISC 33
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#define CLKID_SPI 34
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#define CLKID_I2S_SPDIF 35
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#define CLKID_ETH 36
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/* #define CLKID_ETH */
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#define CLKID_DEMUX 37
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#define CLKID_AIU_GLUE 38
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#define CLKID_IEC958 39
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@ -114,12 +114,12 @@
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#define CLKID_AIU 47
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#define CLKID_UART1 48
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#define CLKID_G2D 49
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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/* #define CLKID_USB0 */
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/* #define CLKID_USB1 */
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#define CLKID_RESET 52
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#define CLKID_NAND 53
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#define CLKID_DOS_PARSER 54
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#define CLKID_USB 55
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/* #define CLKID_USB */
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#define CLKID_VDIN1 56
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#define CLKID_AHB_ARB0 57
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#define CLKID_EFUSE 58
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@ -128,12 +128,12 @@
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#define CLKID_AHB_CTRL_BUS 61
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#define CLKID_HDMI_INTR_SYNC 62
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#define CLKID_HDMI_PCLK 63
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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/* CLKID_USB1_DDR_BRIDGE */
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/* CLKID_USB0_DDR_BRIDGE */
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#define CLKID_MMC_PCLK 66
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#define CLKID_DVIN 67
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#define CLKID_UART2 68
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#define CLKID_SANA 69
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/* #define CLKID_SANA */
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#define CLKID_VPU_INTR 70
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#define CLKID_SEC_AHB_AHB3_BRIDGE 71
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#define CLKID_CLK81_A9 72
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@ -21,5 +21,15 @@
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#define CLKID_ZERO 13
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#define CLKID_MPEG_SEL 14
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#define CLKID_MPEG_DIV 15
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#define CLKID_SAR_ADC 23
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#define CLKID_RNG0 25
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#define CLKID_SDIO 30
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#define CLKID_ETH 36
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_USB 55
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_SANA 69
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#endif /* __MESON8B_CLKC_H */
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