x86, dax, libnvdimm: remove wb_cache_pmem() indirection
With all handling of the CONFIG_ARCH_HAS_PMEM_API case being moved to libnvdimm and the pmem driver directly we do not need to provide global wrappers and fallbacks in the CONFIG_ARCH_HAS_PMEM_API=n case. The pmem driver will simply not link to arch_wb_cache_pmem() in that case. Same as before, pmem flushing is only defined for x86_64, via clean_cache_range(), but it is straightforward to add other archs in the future. arch_wb_cache_pmem() is an exported function since the pmem module needs to find it, but it is privately declared in drivers/nvdimm/pmem.h because there are no consumers outside of the pmem driver. Cc: <x86@kernel.org> Cc: Jan Kara <jack@suse.cz> Cc: Jeff Moyer <jmoyer@redhat.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Oliver O'Halloran <oohall@gmail.com> Cc: Matthew Wilcox <mawilcox@microsoft.com> Cc: Ross Zwisler <ross.zwisler@linux.intel.com> Suggested-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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@ -44,27 +44,6 @@ static inline void arch_memcpy_to_pmem(void *dst, const void *src, size_t n)
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BUG();
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}
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/**
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* arch_wb_cache_pmem - write back a cache range with CLWB
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* @vaddr: virtual start address
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* @size: number of bytes to write back
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*
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* Write back a cache range using the CLWB (cache line write back)
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* instruction. Note that @size is internally rounded up to be cache
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* line size aligned.
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*/
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static inline void arch_wb_cache_pmem(void *addr, size_t size)
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{
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u16 x86_clflush_size = boot_cpu_data.x86_clflush_size;
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unsigned long clflush_mask = x86_clflush_size - 1;
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void *vend = addr + size;
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void *p;
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for (p = (void *)((unsigned long)addr & ~clflush_mask);
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p < vend; p += x86_clflush_size)
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clwb(p);
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}
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static inline void arch_invalidate_pmem(void *addr, size_t size)
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{
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clflush_cache_range(addr, size);
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@ -97,6 +97,12 @@ static void clean_cache_range(void *addr, size_t size)
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clwb(p);
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}
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void arch_wb_cache_pmem(void *addr, size_t size)
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{
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clean_cache_range(addr, size);
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}
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EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);
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long __copy_user_flushcache(void *dst, const void __user *src, unsigned size)
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{
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unsigned long flushed, dest = (unsigned long) dst;
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@ -245,7 +245,7 @@ static size_t pmem_copy_from_iter(struct dax_device *dax_dev, pgoff_t pgoff,
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static void pmem_dax_flush(struct dax_device *dax_dev, pgoff_t pgoff,
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void *addr, size_t size)
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{
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wb_cache_pmem(addr, size);
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arch_wb_cache_pmem(addr, size);
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}
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static const struct dax_operations pmem_dax_ops = {
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@ -5,6 +5,14 @@
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#include <linux/pfn_t.h>
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#include <linux/fs.h>
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#ifdef CONFIG_ARCH_HAS_PMEM_API
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void arch_wb_cache_pmem(void *addr, size_t size);
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#else
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static inline void arch_wb_cache_pmem(void *addr, size_t size)
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{
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}
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#endif
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/* this definition is in it's own header for tools/testing/nvdimm to consume */
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struct pmem_device {
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/* One contiguous memory region per device */
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@ -31,11 +31,6 @@ static inline void arch_memcpy_to_pmem(void *dst, const void *src, size_t n)
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BUG();
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}
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static inline void arch_wb_cache_pmem(void *addr, size_t size)
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{
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BUG();
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}
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static inline void arch_invalidate_pmem(void *addr, size_t size)
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{
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BUG();
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@ -80,18 +75,4 @@ static inline void invalidate_pmem(void *addr, size_t size)
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if (arch_has_pmem_api())
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arch_invalidate_pmem(addr, size);
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}
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/**
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* wb_cache_pmem - write back processor cache for PMEM memory range
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* @addr: virtual start address
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* @size: number of bytes to write back
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*
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* Write back the processor cache range starting at 'addr' for 'size' bytes.
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* See blkdev_issue_flush() note for memcpy_to_pmem().
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*/
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static inline void wb_cache_pmem(void *addr, size_t size)
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{
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if (arch_has_pmem_api())
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arch_wb_cache_pmem(addr, size);
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}
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#endif /* __PMEM_H__ */
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