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drm/v3d: Don't clear MMU control bits on exception

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MMU exception conditions are reported in the V3D_MMU_CTRL register as
write-1-to-clear (W1C) bits. The MMU interrupt handling code clears any
exceptions, but does so by masking out any other bits and writing the
result back. There are some important control bits in that register,
including MMU_ENABLE, so a safer approach is to simply write back the
value just read unaltered.

Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/1608755714-18233-4-git-send-email-stefan.wahren@i2se.com
This commit is contained in:
Phil Elwell 2020-12-23 21:35:13 +01:00 committed by Maxime Ripard
parent 334dd38a38
commit 545d9d7802
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GPG Key ID: E3EF0D6F671851C5
1 changed files with 1 additions and 4 deletions
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5
drivers/gpu/drm/v3d/v3d_irq.c
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@ -178,10 +178,7 @@ v3d_hub_irq(int irq, void *arg)
};
const char *client = "?";
V3D_WRITE(V3D_MMU_CTL,
V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED |
V3D_MMU_CTL_PT_INVALID |
V3D_MMU_CTL_WRITE_VIOLATION));
V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
if (v3d->ver >= 41) {
axi_id = axi_id >> 5;