powerpc: Add memory management headers for new 64-bit BookE
This adds the PTE and pgtable format definitions, along with changes to the kernel memory map and other definitions related to implementing support for 64-bit Book3E. This also shields some asm-offset bits that are currently only relevant on 32-bit We also move the definition of the "linux" page size constants to the common mmu.h file and add a few sizes that are relevant to embedded processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
parent
0257c99cdf
commit
57e2a99f74
@ -170,6 +170,33 @@ typedef struct {
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unsigned int active;
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unsigned long vdso_base;
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} mm_context_t;
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/* Page size definitions, common between 32 and 64-bit
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*
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* shift : is the "PAGE_SHIFT" value for that page size
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* penc : is the pte encoding mask
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*
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*/
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struct mmu_psize_def
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{
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unsigned int shift; /* number of bits */
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unsigned int enc; /* PTE encoding */
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};
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extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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/* The page sizes use the same names as 64-bit hash but are
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* constants
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*/
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#if defined(CONFIG_PPC_4K_PAGES)
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#define mmu_virtual_psize MMU_PAGE_4K
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#elif defined(CONFIG_PPC_64K_PAGES)
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#define mmu_virtual_psize MMU_PAGE_64K
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#else
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#error Unsupported page size
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#endif
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extern int mmu_linear_psize;
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
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@ -138,26 +138,6 @@ struct mmu_psize_def
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#endif /* __ASSEMBLY__ */
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/*
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* The kernel use the constants below to index in the page sizes array.
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* The use of fixed constants for this purpose is better for performances
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* of the low level hash refill handlers.
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*
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* A non supported page size has a "shift" field set to 0
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*
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* Any new page size being implemented can get a new entry in here. Whether
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* the kernel will use it or not is a different matter though. The actual page
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* size used by hugetlbfs is not defined here and may be made variable
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*/
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#define MMU_PAGE_4K 0 /* 4K */
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#define MMU_PAGE_64K 1 /* 64K */
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#define MMU_PAGE_64K_AP 2 /* 64K Admixed (in a 4K segment) */
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#define MMU_PAGE_1M 3 /* 1M */
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#define MMU_PAGE_16M 4 /* 16M */
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#define MMU_PAGE_16G 5 /* 16G */
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#define MMU_PAGE_COUNT 6
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/*
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* Segment sizes.
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* These are the values used by hardware in the B field of
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@ -17,6 +17,7 @@
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#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
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#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
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#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
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#define MMU_FTR_TYPE_3E ASM_CONST(0x00000020)
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/*
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* This is individual features
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@ -73,6 +74,41 @@ extern void early_init_mmu_secondary(void);
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#endif /* !__ASSEMBLY__ */
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/* The kernel use the constants below to index in the page sizes array.
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* The use of fixed constants for this purpose is better for performances
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* of the low level hash refill handlers.
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*
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* A non supported page size has a "shift" field set to 0
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*
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* Any new page size being implemented can get a new entry in here. Whether
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* the kernel will use it or not is a different matter though. The actual page
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* size used by hugetlbfs is not defined here and may be made variable
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*
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* Note: This array ended up being a false good idea as it's growing to the
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* point where I wonder if we should replace it with something different,
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* to think about, feedback welcome. --BenH.
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*/
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/* There are #define as they have to be used in assembly
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*
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* WARNING: If you change this list, make sure to update the array of
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* names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
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* happen
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*/
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#define MMU_PAGE_4K 0
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#define MMU_PAGE_16K 1
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#define MMU_PAGE_64K 2
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#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
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#define MMU_PAGE_256K 4
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#define MMU_PAGE_1M 5
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#define MMU_PAGE_8M 6
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#define MMU_PAGE_16M 7
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#define MMU_PAGE_256M 8
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#define MMU_PAGE_1G 9
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#define MMU_PAGE_16G 10
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#define MMU_PAGE_64G 11
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#define MMU_PAGE_COUNT 12
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#if defined(CONFIG_PPC_STD_MMU_64)
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/* 64-bit classic hash table MMU */
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@ -94,5 +130,6 @@ extern void early_init_mmu_secondary(void);
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# include <asm/mmu-8xx.h>
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_MMU_H_ */
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@ -139,7 +139,11 @@ extern phys_addr_t kernstart_addr;
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* Don't compare things with KERNELBASE or PAGE_OFFSET to test for
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* "kernelness", use is_kernel_addr() - it should do what you want.
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*/
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#ifdef CONFIG_PPC_BOOK3E_64
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#define is_kernel_addr(x) ((x) >= 0x8000000000000000ul)
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#else
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#define is_kernel_addr(x) ((x) >= PAGE_OFFSET)
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#endif
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#ifndef __ASSEMBLY__
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@ -135,12 +135,22 @@ extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
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#endif /* __ASSEMBLY__ */
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#else
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#define slice_init()
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#ifdef CONFIG_PPC_STD_MMU_64
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#define get_slice_psize(mm, addr) ((mm)->context.user_psize)
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#define slice_set_user_psize(mm, psize) \
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do { \
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(mm)->context.user_psize = (psize); \
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(mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
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} while (0)
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#else /* CONFIG_PPC_STD_MMU_64 */
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#ifdef CONFIG_PPC_64K_PAGES
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#define get_slice_psize(mm, addr) MMU_PAGE_64K
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#else /* CONFIG_PPC_64K_PAGES */
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#define get_slice_psize(mm, addr) MMU_PAGE_4K
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#endif /* !CONFIG_PPC_64K_PAGES */
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#define slice_set_user_psize(mm, psize) do { BUG(); } while(0)
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#endif /* !CONFIG_PPC_STD_MMU_64 */
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#define slice_set_range_psize(mm, start, len, psize) \
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slice_set_user_psize((mm), (psize))
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#define slice_mm_new_context(mm) 1
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@ -5,11 +5,6 @@
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* the ppc64 hashed page table.
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*/
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#ifndef __ASSEMBLY__
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#include <linux/stddef.h>
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#include <asm/tlbflush.h>
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_PPC_64K_PAGES
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#include <asm/pgtable-ppc64-64k.h>
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#else
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@ -38,26 +33,46 @@
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#endif
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/*
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* Define the address range of the vmalloc VM area.
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* Define the address range of the kernel non-linear virtual area
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*/
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#define VMALLOC_START ASM_CONST(0xD000000000000000)
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#define VMALLOC_SIZE (PGTABLE_RANGE >> 1)
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#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
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#ifdef CONFIG_PPC_BOOK3E
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#define KERN_VIRT_START ASM_CONST(0x8000000000000000)
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#else
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#define KERN_VIRT_START ASM_CONST(0xD000000000000000)
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#endif
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#define KERN_VIRT_SIZE PGTABLE_RANGE
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/*
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* Define the address ranges for MMIO and IO space :
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* The vmalloc space starts at the beginning of that region, and
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* occupies half of it on hash CPUs and a quarter of it on Book3E
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*/
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#define VMALLOC_START KERN_VIRT_START
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#ifdef CONFIG_PPC_BOOK3E
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#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 2)
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#else
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#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
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#endif
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#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
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/*
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* The second half of the kernel virtual space is used for IO mappings,
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* it's itself carved into the PIO region (ISA and PHB IO space) and
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* the ioremap space
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*
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* ISA_IO_BASE = VMALLOC_END, 64K reserved area
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* ISA_IO_BASE = KERN_IO_START, 64K reserved area
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* PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
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* IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
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*/
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#define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
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#define FULL_IO_SIZE 0x80000000ul
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#define ISA_IO_BASE (VMALLOC_END)
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#define ISA_IO_END (VMALLOC_END + 0x10000ul)
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#define ISA_IO_BASE (KERN_IO_START)
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#define ISA_IO_END (KERN_IO_START + 0x10000ul)
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#define PHB_IO_BASE (ISA_IO_END)
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#define PHB_IO_END (VMALLOC_END + FULL_IO_SIZE)
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#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
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#define IOREMAP_BASE (PHB_IO_END)
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#define IOREMAP_END (VMALLOC_START + PGTABLE_RANGE)
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#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
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/*
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* Region IDs
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@ -72,19 +87,28 @@
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#define USER_REGION_ID (0UL)
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/*
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* Defines the address of the vmemap area, in its own region
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* Defines the address of the vmemap area, in its own region on
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* hash table CPUs and after the vmalloc space on Book3E
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*/
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#ifdef CONFIG_PPC_BOOK3E
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#define VMEMMAP_BASE VMALLOC_END
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#define VMEMMAP_END KERN_IO_START
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#else
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#define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT)
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#endif
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#define vmemmap ((struct page *)VMEMMAP_BASE)
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/*
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* Include the PTE bits definitions
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*/
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#ifdef CONFIG_PPC_BOOK3S
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#include <asm/pte-hash64.h>
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#else
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#include <asm/pte-book3e.h>
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#endif
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#include <asm/pte-common.h>
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#ifdef CONFIG_PPC_MM_SLICES
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#define HAVE_ARCH_UNMAPPED_AREA
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#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
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@ -92,6 +116,9 @@
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#ifndef __ASSEMBLY__
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#include <linux/stddef.h>
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#include <asm/tlbflush.h>
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/*
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* This is the default implementation of various PTE accessors, it's
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* used in all cases except Book3S with 64K pages where we have a
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70
arch/powerpc/include/asm/pte-book3e.h
Normal file
70
arch/powerpc/include/asm/pte-book3e.h
Normal file
@ -0,0 +1,70 @@
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#ifndef _ASM_POWERPC_PTE_BOOK3E_H
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#define _ASM_POWERPC_PTE_BOOK3E_H
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#ifdef __KERNEL__
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/* PTE bit definitions for processors compliant to the Book3E
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* architecture 2.06 or later. The position of the PTE bits
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* matches the HW definition of the optional Embedded Page Table
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* category.
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*/
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/* Architected bits */
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#define _PAGE_PRESENT 0x000001 /* software: pte contains a translation */
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#define _PAGE_FILE 0x000002 /* (!present only) software: pte holds file offset */
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#define _PAGE_SW1 0x000002
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#define _PAGE_BAP_SR 0x000004
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#define _PAGE_BAP_UR 0x000008
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#define _PAGE_BAP_SW 0x000010
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#define _PAGE_BAP_UW 0x000020
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#define _PAGE_BAP_SX 0x000040
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#define _PAGE_BAP_UX 0x000080
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#define _PAGE_PSIZE_MSK 0x000f00
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#define _PAGE_PSIZE_4K 0x000200
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#define _PAGE_PSIZE_64K 0x000600
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#define _PAGE_PSIZE_1M 0x000a00
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#define _PAGE_PSIZE_16M 0x000e00
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#define _PAGE_DIRTY 0x001000 /* C: page changed */
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#define _PAGE_SW0 0x002000
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#define _PAGE_U3 0x004000
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#define _PAGE_U2 0x008000
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#define _PAGE_U1 0x010000
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#define _PAGE_U0 0x020000
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#define _PAGE_ACCESSED 0x040000
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#define _PAGE_LENDIAN 0x080000
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#define _PAGE_GUARDED 0x100000
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#define _PAGE_COHERENT 0x200000 /* M: enforce memory coherence */
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#define _PAGE_NO_CACHE 0x400000 /* I: cache inhibit */
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#define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */
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/* "Higher level" linux bit combinations */
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#define _PAGE_EXEC _PAGE_BAP_SX /* Can be executed from potentially */
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#define _PAGE_HWEXEC _PAGE_BAP_UX /* .. and was cache cleaned */
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#define _PAGE_RW (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
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#define _PAGE_KERNEL_RW (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
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#define _PAGE_KERNEL_RO (_PAGE_BAP_SR)
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#define _PAGE_USER (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
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#define _PAGE_HASHPTE 0
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#define _PAGE_BUSY 0
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#define _PAGE_SPECIAL _PAGE_SW0
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/* Flags to be preserved on PTE modifications */
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#define _PAGE_HPTEFLAGS _PAGE_BUSY
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/* Base page size */
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#ifdef CONFIG_PPC_64K_PAGES
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#define _PAGE_PSIZE _PAGE_PSIZE_64K
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#define PTE_RPN_SHIFT (28)
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#else
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#define _PAGE_PSIZE _PAGE_PSIZE_4K
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#define PTE_RPN_SHIFT (24)
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#endif
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/* On 32-bit, we never clear the top part of the PTE */
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#ifdef CONFIG_PPC32
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#define _PTE_NONE_MASK 0xffffffff00000000ULL
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PTE_FSL_BOOKE_H */
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@ -34,6 +34,9 @@
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#ifndef _PAGE_4K_PFN
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#define _PAGE_4K_PFN 0
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#endif
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#ifndef _PAGE_SAO
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#define _PAGE_SAO 0
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#endif
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#ifndef _PAGE_PSIZE
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#define _PAGE_PSIZE 0
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#endif
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@ -52,9 +52,11 @@
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#include <linux/kvm_host.h>
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#endif
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#ifdef CONFIG_PPC32
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#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
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#include "head_booke.h"
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#endif
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#endif
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#if defined(CONFIG_FSL_BOOKE)
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#include "../mm/mmu_decl.h"
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@ -260,6 +262,7 @@ int main(void)
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DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8);
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#endif /* CONFIG_PPC64 */
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#if defined(CONFIG_PPC32)
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#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
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DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
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DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
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@ -278,7 +281,7 @@ int main(void)
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DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
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DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
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#endif
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#endif
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DEFINE(CLONE_VM, CLONE_VM);
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DEFINE(CLONE_UNTRACED, CLONE_UNTRACED);
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@ -57,8 +57,10 @@ unsigned int mmu_huge_psizes[MMU_PAGE_COUNT] = { }; /* initialize all to 0 */
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#define HUGEPTE_CACHE_NAME(psize) (huge_pgtable_cache_name[psize])
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static const char *huge_pgtable_cache_name[MMU_PAGE_COUNT] = {
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"unused_4K", "hugepte_cache_64K", "unused_64K_AP",
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"hugepte_cache_1M", "hugepte_cache_16M", "hugepte_cache_16G"
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[MMU_PAGE_64K] = "hugepte_cache_64K",
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[MMU_PAGE_1M] = "hugepte_cache_1M",
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[MMU_PAGE_16M] = "hugepte_cache_16M",
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[MMU_PAGE_16G] = "hugepte_cache_16G",
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};
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/* Flag to mark huge PD pointers. This means pmd_bad() and pud_bad()
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@ -700,6 +702,8 @@ static void __init set_huge_psize(int psize)
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if (mmu_huge_psizes[psize] ||
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mmu_psize_defs[psize].shift == PAGE_SHIFT)
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return;
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if (WARN_ON(HUGEPTE_CACHE_NAME(psize) == NULL))
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return;
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hugetlb_add_hstate(mmu_psize_defs[psize].shift - PAGE_SHIFT);
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switch (mmu_psize_defs[psize].shift) {
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