arm64: dts: qcom: sc7180: Update dts for DP phy inside QMP phy
Drop the old node and add the new one in its place. Cc: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Rob Clark <robdclark@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> [dianders: Adjusted due to DP not itself not in upstream dts yet] Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.1.Iad06142ceb8426ce5492737bf3d9162ed0dd2b55@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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@ -2770,12 +2770,11 @@
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};
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usb_1_qmpphy: phy-wrapper@88e9000 {
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compatible = "qcom,sc7180-qmp-usb3-phy";
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compatible = "qcom,sc7180-qmp-usb3-dp-phy";
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reg = <0 0x088e9000 0 0x18c>,
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<0 0x088e8000 0 0x38>;
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reg-names = "reg-base", "dp_com";
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<0 0x088e8000 0 0x38>,
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<0 0x088ea000 0 0x40>;
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status = "disabled";
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#clock-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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@ -2790,7 +2789,7 @@
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<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
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reset-names = "phy", "common";
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usb_1_ssphy: phy@88e9200 {
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usb_1_ssphy: usb3-phy@88e9200 {
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reg = <0 0x088e9200 0 0x128>,
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<0 0x088e9400 0 0x200>,
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<0 0x088e9c00 0 0x218>,
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@ -2803,6 +2802,16 @@
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clock-names = "pipe0";
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clock-output-names = "usb3_phy_pipe_clk_src";
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};
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dp_phy: dp-phy@88ea200 {
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reg = <0 0x088ea200 0 0x200>,
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<0 0x088ea400 0 0x200>,
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<0 0x088eaa00 0 0x200>,
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<0 0x088ea600 0 0x200>,
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<0 0x088ea800 0 0x200>;
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#clock-cells = <1>;
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#phy-cells = <0>;
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};
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};
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dc_noc: interconnect@9160000 {
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@ -3166,8 +3175,8 @@
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<&gcc GCC_DISP_GPLL0_CLK_SRC>,
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<&dsi_phy 0>,
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<&dsi_phy 1>,
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<0>,
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<0>;
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<&dp_phy 0>,
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<&dp_phy 1>;
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clock-names = "bi_tcxo",
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"gcc_disp_gpll0_clk_src",
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"dsi0_phy_pll_out_byteclk",
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