clk: Add clock driver for ASPEED BMC SoCs
This adds the stub of a driver for the ASPEED SoCs. The clocks are defined and the static registration is set up. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Joel Stanley
Stephen Boyd
parent
ae50ff7b6d
commit
5eda5d79e4
@ -142,6 +142,18 @@ config COMMON_CLK_GEMINI
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This driver supports the SoC clocks on the Cortina Systems Gemini
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platform, also known as SL3516 or CS3516.
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config COMMON_CLK_ASPEED
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bool "Clock driver for Aspeed BMC SoCs"
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depends on ARCH_ASPEED || COMPILE_TEST
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default ARCH_ASPEED
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select MFD_SYSCON
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select RESET_CONTROLLER
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---help---
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This driver supports the SoC clocks on the Aspeed BMC platforms.
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The G4 and G5 series, including the ast2400 and ast2500, are supported
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by this driver.
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config COMMON_CLK_S2MPS11
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tristate "Clock driver for S2MPS1X/S5M8767 MFD"
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depends on MFD_SEC_CORE || COMPILE_TEST
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@ -27,6 +27,7 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
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obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
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obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
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obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
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obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
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obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
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obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
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obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
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141
drivers/clk/clk-aspeed.c
Normal file
141
drivers/clk/clk-aspeed.c
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@ -0,0 +1,141 @@
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// SPDX-License-Identifier: GPL-2.0+
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#define pr_fmt(fmt) "clk-aspeed: " fmt
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <dt-bindings/clock/aspeed-clock.h>
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#define ASPEED_NUM_CLKS 35
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#define ASPEED_STRAP 0x70
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/* Keeps track of all clocks */
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static struct clk_hw_onecell_data *aspeed_clk_data;
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static void __iomem *scu_base;
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/**
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* struct aspeed_gate_data - Aspeed gated clocks
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* @clock_idx: bit used to gate this clock in the clock register
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* @reset_idx: bit used to reset this IP in the reset register. -1 if no
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* reset is required when enabling the clock
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* @name: the clock name
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* @parent_name: the name of the parent clock
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* @flags: standard clock framework flags
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*/
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struct aspeed_gate_data {
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u8 clock_idx;
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s8 reset_idx;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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};
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/**
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* struct aspeed_clk_gate - Aspeed specific clk_gate structure
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register controlling gate
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* @clock_idx: bit used to gate this clock in the clock register
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* @reset_idx: bit used to reset this IP in the reset register. -1 if no
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* reset is required when enabling the clock
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* @flags: hardware-specific flags
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* @lock: register lock
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*
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* Some of the clocks in the Aspeed SoC must be put in reset before enabling.
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* This modified version of clk_gate allows an optional reset bit to be
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* specified.
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*/
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struct aspeed_clk_gate {
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struct clk_hw hw;
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struct regmap *map;
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u8 clock_idx;
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s8 reset_idx;
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u8 flags;
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spinlock_t *lock;
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};
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#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
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/* TODO: ask Aspeed about the actual parent data */
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static const struct aspeed_gate_data aspeed_gates[] = {
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/* clk rst name parent flags */
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[ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
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[ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
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[ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
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[ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
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[ASPEED_CLK_GATE_BCLK] = { 4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
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[ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */
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[ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
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[ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
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[ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */
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[ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
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[ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */
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[ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
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[ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
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[ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
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[ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
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[ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
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[ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
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[ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */
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[ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */
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[ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */
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[ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
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[ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
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[ASPEED_CLK_GATE_SDCLKCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
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[ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
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};
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static void __init aspeed_cc_init(struct device_node *np)
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{
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struct regmap *map;
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u32 val;
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int ret;
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int i;
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scu_base = of_iomap(np, 0);
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if (IS_ERR(scu_base))
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return;
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aspeed_clk_data = kzalloc(sizeof(*aspeed_clk_data) +
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sizeof(*aspeed_clk_data->hws) * ASPEED_NUM_CLKS,
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GFP_KERNEL);
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if (!aspeed_clk_data)
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return;
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/*
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* This way all clocks fetched before the platform device probes,
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* except those we assign here for early use, will be deferred.
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*/
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for (i = 0; i < ASPEED_NUM_CLKS; i++)
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aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
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map = syscon_node_to_regmap(np);
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if (IS_ERR(map)) {
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pr_err("no syscon regmap\n");
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return;
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}
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/*
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* We check that the regmap works on this very first access,
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* but as this is an MMIO-backed regmap, subsequent regmap
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* access is not going to fail and we skip error checks from
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* this point.
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*/
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ret = regmap_read(map, ASPEED_STRAP, &val);
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if (ret) {
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pr_err("failed to read strapping register\n");
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return;
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}
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aspeed_clk_data->num = ASPEED_NUM_CLKS;
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ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
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if (ret)
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pr_err("failed to add DT provider: %d\n", ret);
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};
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CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init);
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CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init);
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