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mt76: mt7663: fix aggr range entry in debugfs

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Fix register definitions for aggr range counter registers for mt7663
chipset

Fixes: f40ac0f3d3c0 ("mt76: mt7615: introduce mt7663e support")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Lorenzo Bianconi 2020-04-08 14:20:39 +02:00 committed by Felix Fietkau
parent 1855ad5360
commit 6bcfdabbad
3 changed files with 10 additions and 2 deletions
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6
drivers/net/wireless/mediatek/mt76/mt7615/debugfs.c
View File

@ -129,16 +129,18 @@ mt7615_ampdu_stat_read_phy(struct mt7615_phy *phy,
struct seq_file *file)
{
struct mt7615_dev *dev = file->private;
u32 reg = is_mt7663(&dev->mt76) ? MT_MIB_ARNG(0) : MT_AGG_ASRCR0;
bool ext_phy = phy != &dev->phy;
int bound[7], i, range;
if (!phy)
return;
range = mt76_rr(dev, MT_AGG_ASRCR0);
range = mt76_rr(dev, reg);
for (i = 0; i < 4; i++)
bound[i] = MT_AGG_ASRCR_RANGE(range, i) + 1;
range = mt76_rr(dev, MT_AGG_ASRCR1);
range = mt76_rr(dev, reg + 4);
for (i = 0; i < 3; i++)
bound[i + 4] = MT_AGG_ASRCR_RANGE(range, i) + 1;

1
drivers/net/wireless/mediatek/mt76/mt7615/init.c
View File

@ -116,6 +116,7 @@ static void mt7615_mac_init(struct mt7615_dev *dev)
mt76_wr(dev, MT_DMA_DCR0,
FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 3072) |
MT_DMA_DCR0_RX_VEC_DROP);
mt76_set(dev, MT_WF_MIB_SCR0, MT_MIB_SCR0_AGG_CNT_RANGE_EN);
if (is_mt7663(&dev->mt76)) {
mt76_wr(dev, MT_WF_AGG(0x160), 0x5c341c02);
mt76_wr(dev, MT_WF_AGG(0x164), 0x70708040);

5
drivers/net/wireless/mediatek/mt76/mt7615/regs.h
View File

@ -384,6 +384,9 @@ enum mt7615_reg_base {
#define MT_WF_MIB_BASE (dev->reg_map[MT_MIB_BASE])
#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE + (ofs) + (_band) * 0x200)
#define MT_WF_MIB_SCR0 MT_WF_MIB(0, 0)
#define MT_MIB_SCR0_AGG_CNT_RANGE_EN BIT(21)
#define MT_MIB_M0_MISC_CR(_band) MT_WF_MIB(_band, 0x00c)
#define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014)
@ -414,6 +417,8 @@ enum mt7615_reg_base {
#define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)
#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
#define MT_MIB_ARNG(n) MT_WF_MIB(0, 0x4b8 + ((n) << 2))
#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0xa8 + ((n) << 2))
#define MT_DMA_SHDL(ofs) (dev->reg_map[MT_DMA_SHDL_BASE] + (ofs))