drm/i915/selftests: Exercise intel_timeline_read_hwsp()
intel_timeline_read_hwsp() is used to support semaphore waits between engines, that may themselves be deferred for arbitrary periods -- that is the read of the target request's HWSP is at an indeterminant point in the future. To support this, we need to prevent overwriting a HWSP that is being watched across a seqno wrap (otherwise the next request will write its value into the old HWSP preventing the watcher from making progress, ad infinitum.) To simulate the observer across a wrap, let's create a request that reads from the HWSP and dispatch it at different points around a wrap to see if the value is lost. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201021220411.5777-2-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
@ -17,8 +17,9 @@
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#include "../selftests/i915_random.h"
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#include "../i915_selftest.h"
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#include "../selftests/igt_flush_test.h"
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#include "../selftests/mock_gem_device.h"
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#include "selftests/igt_flush_test.h"
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#include "selftests/lib_sw_fence.h"
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#include "selftests/mock_gem_device.h"
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#include "selftests/mock_timeline.h"
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static struct page *hwsp_page(struct intel_timeline *tl)
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@ -755,6 +756,378 @@ out_free:
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return err;
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}
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static int emit_read_hwsp(struct i915_request *rq,
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u32 seqno, u32 hwsp,
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u32 *addr)
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{
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const u32 gpr = i915_mmio_reg_offset(GEN8_RING_CS_GPR(rq->engine->mmio_base, 0));
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u32 *cs;
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cs = intel_ring_begin(rq, 12);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
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*cs++ = *addr;
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*cs++ = 0;
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*cs++ = seqno;
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*addr += 4;
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*cs++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_USE_GGTT;
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*cs++ = gpr;
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*cs++ = hwsp;
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*cs++ = 0;
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*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
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*cs++ = gpr;
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*cs++ = *addr;
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*cs++ = 0;
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*addr += 4;
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intel_ring_advance(rq, cs);
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return 0;
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}
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struct hwsp_watcher {
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struct i915_vma *vma;
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struct i915_request *rq;
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u32 addr;
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u32 *map;
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};
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static bool cmp_lt(u32 a, u32 b)
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{
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return a < b;
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}
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static bool cmp_gte(u32 a, u32 b)
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{
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return a >= b;
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}
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static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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obj = i915_gem_object_create_internal(gt->i915, SZ_2M);
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if (IS_ERR(obj))
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return PTR_ERR(obj);
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w->map = i915_gem_object_pin_map(obj, I915_MAP_WB);
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if (IS_ERR(w->map)) {
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i915_gem_object_put(obj);
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return PTR_ERR(w->map);
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}
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vma = i915_gem_object_ggtt_pin_ww(obj, NULL, NULL, 0, 0, 0);
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if (IS_ERR(vma)) {
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i915_gem_object_put(obj);
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return PTR_ERR(vma);
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}
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w->vma = vma;
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w->addr = i915_ggtt_offset(vma);
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return 0;
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}
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static int create_watcher(struct hwsp_watcher *w,
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struct intel_engine_cs *engine,
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int ringsz)
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{
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struct intel_context *ce;
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struct intel_timeline *tl;
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ce = intel_context_create(engine);
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if (IS_ERR(ce))
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return PTR_ERR(ce);
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ce->ring = __intel_context_ring_size(ringsz);
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w->rq = intel_context_create_request(ce);
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intel_context_put(ce);
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if (IS_ERR(w->rq))
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return PTR_ERR(w->rq);
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w->addr = i915_ggtt_offset(w->vma);
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tl = w->rq->context->timeline;
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/* some light mutex juggling required; think co-routines */
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lockdep_unpin_lock(&tl->mutex, w->rq->cookie);
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mutex_unlock(&tl->mutex);
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return 0;
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}
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static int check_watcher(struct hwsp_watcher *w, const char *name,
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bool (*op)(u32 hwsp, u32 seqno))
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{
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struct i915_request *rq = fetch_and_zero(&w->rq);
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struct intel_timeline *tl = rq->context->timeline;
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u32 offset, end;
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int err;
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GEM_BUG_ON(w->addr - i915_ggtt_offset(w->vma) > w->vma->size);
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i915_request_get(rq);
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mutex_lock(&tl->mutex);
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rq->cookie = lockdep_pin_lock(&tl->mutex);
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i915_request_add(rq);
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if (i915_request_wait(rq, 0, HZ) < 0) {
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err = -ETIME;
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goto out;
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}
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err = 0;
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offset = 0;
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end = (w->addr - i915_ggtt_offset(w->vma)) / sizeof(*w->map);
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while (offset < end) {
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if (!op(w->map[offset + 1], w->map[offset])) {
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pr_err("Watcher '%s' found HWSP value %x for seqno %x\n",
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name, w->map[offset + 1], w->map[offset]);
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err = -EINVAL;
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}
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offset += 2;
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}
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out:
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i915_request_put(rq);
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return err;
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}
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static void cleanup_watcher(struct hwsp_watcher *w)
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{
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if (w->rq) {
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struct intel_timeline *tl = w->rq->context->timeline;
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mutex_lock(&tl->mutex);
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w->rq->cookie = lockdep_pin_lock(&tl->mutex);
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i915_request_add(w->rq);
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}
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i915_vma_unpin_and_release(&w->vma, I915_VMA_RELEASE_MAP);
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}
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static bool retire_requests(struct intel_timeline *tl)
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{
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struct i915_request *rq, *rn;
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mutex_lock(&tl->mutex);
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list_for_each_entry_safe(rq, rn, &tl->requests, link)
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if (!i915_request_retire(rq))
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break;
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mutex_unlock(&tl->mutex);
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return !i915_active_fence_isset(&tl->last_request);
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}
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static struct i915_request *wrap_timeline(struct i915_request *rq)
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{
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struct intel_context *ce = rq->context;
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struct intel_timeline *tl = ce->timeline;
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u32 seqno = rq->fence.seqno;
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while (tl->seqno >= seqno) { /* Cause a wrap */
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i915_request_put(rq);
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq))
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return rq;
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i915_request_get(rq);
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i915_request_add(rq);
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}
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i915_request_put(rq);
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq))
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return rq;
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i915_request_get(rq);
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i915_request_add(rq);
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return rq;
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}
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static int live_hwsp_read(void *arg)
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{
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struct intel_gt *gt = arg;
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struct hwsp_watcher watcher[2] = {};
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struct intel_engine_cs *engine;
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struct intel_timeline *tl;
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enum intel_engine_id id;
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int err = 0;
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int i;
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/*
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* If we take a reference to the HWSP for reading on the GPU, that
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* read may be arbitrarily delayed (either by foreign fence or
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* priority saturation) and a wrap can happen within 30 minutes.
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* When the GPU read is finally submitted it should be correct,
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* even across multiple wraps.
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*/
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if (INTEL_GEN(gt->i915) < 8) /* CS convenience [SRM/LRM] */
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return 0;
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tl = intel_timeline_create(gt);
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if (IS_ERR(tl))
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return PTR_ERR(tl);
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if (!tl->hwsp_cacheline)
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goto out_free;
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for (i = 0; i < ARRAY_SIZE(watcher); i++) {
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err = setup_watcher(&watcher[i], gt);
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if (err)
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goto out;
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}
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for_each_engine(engine, gt, id) {
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struct intel_context *ce;
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unsigned long count = 0;
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IGT_TIMEOUT(end_time);
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/* Create a request we can use for remote reading of the HWSP */
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err = create_watcher(&watcher[1], engine, SZ_512K);
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if (err)
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goto out;
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do {
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struct i915_sw_fence *submit;
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struct i915_request *rq;
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u32 hwsp;
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submit = heap_fence_create(GFP_KERNEL);
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if (!submit) {
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err = -ENOMEM;
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goto out;
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}
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err = create_watcher(&watcher[0], engine, SZ_4K);
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if (err)
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goto out;
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ce = intel_context_create(engine);
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if (IS_ERR(ce)) {
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err = PTR_ERR(ce);
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goto out;
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}
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/* Skip to the end, saving 30 minutes of nops */
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tl->seqno = -10u + 2 * (count & 3);
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WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);
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ce->timeline = intel_timeline_get(tl);
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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intel_context_put(ce);
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goto out;
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}
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err = i915_sw_fence_await_dma_fence(&rq->submit,
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&watcher[0].rq->fence, 0,
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GFP_KERNEL);
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if (err < 0) {
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i915_request_add(rq);
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intel_context_put(ce);
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goto out;
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}
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mutex_lock(&watcher[0].rq->context->timeline->mutex);
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err = intel_timeline_read_hwsp(rq, watcher[0].rq, &hwsp);
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if (err == 0)
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err = emit_read_hwsp(watcher[0].rq, /* before */
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rq->fence.seqno, hwsp,
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&watcher[0].addr);
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mutex_unlock(&watcher[0].rq->context->timeline->mutex);
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if (err) {
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i915_request_add(rq);
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intel_context_put(ce);
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goto out;
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}
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mutex_lock(&watcher[1].rq->context->timeline->mutex);
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err = intel_timeline_read_hwsp(rq, watcher[1].rq, &hwsp);
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if (err == 0)
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err = emit_read_hwsp(watcher[1].rq, /* after */
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rq->fence.seqno, hwsp,
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&watcher[1].addr);
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mutex_unlock(&watcher[1].rq->context->timeline->mutex);
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if (err) {
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i915_request_add(rq);
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intel_context_put(ce);
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goto out;
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}
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i915_request_get(rq);
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i915_request_add(rq);
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rq = wrap_timeline(rq);
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intel_context_put(ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto out;
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}
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err = i915_sw_fence_await_dma_fence(&watcher[1].rq->submit,
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&rq->fence, 0,
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GFP_KERNEL);
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if (err < 0) {
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i915_request_put(rq);
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goto out;
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}
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err = check_watcher(&watcher[0], "before", cmp_lt);
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i915_sw_fence_commit(submit);
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heap_fence_put(submit);
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if (err) {
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i915_request_put(rq);
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goto out;
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}
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count++;
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if (8 * watcher[1].rq->ring->emit >
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3 * watcher[1].rq->ring->size) {
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i915_request_put(rq);
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break;
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}
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/* Flush the timeline before manually wrapping again */
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if (i915_request_wait(rq,
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I915_WAIT_INTERRUPTIBLE,
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HZ) < 0) {
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err = -ETIME;
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i915_request_put(rq);
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goto out;
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}
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retire_requests(tl);
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i915_request_put(rq);
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} while (!__igt_timeout(end_time, NULL));
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WRITE_ONCE(*(u32 *)tl->hwsp_seqno, 0xdeadbeef);
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pr_info("%s: simulated %lu wraps\n", engine->name, count);
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err = check_watcher(&watcher[1], "after", cmp_gte);
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if (err)
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goto out;
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}
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out:
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for (i = 0; i < ARRAY_SIZE(watcher); i++)
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cleanup_watcher(&watcher[i]);
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if (igt_flush_test(gt->i915))
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err = -EIO;
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out_free:
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intel_timeline_put(tl);
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return err;
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}
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static int live_hwsp_rollover_kernel(void *arg)
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{
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struct intel_gt *gt = arg;
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@ -998,6 +1371,7 @@ int intel_timeline_live_selftests(struct drm_i915_private *i915)
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SUBTEST(live_hwsp_engine),
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SUBTEST(live_hwsp_alternate),
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SUBTEST(live_hwsp_wrap),
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SUBTEST(live_hwsp_read),
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SUBTEST(live_hwsp_rollover_kernel),
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SUBTEST(live_hwsp_rollover_user),
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};
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Block a user