drm/amdgpu: Fix channel_index table layout for Aldebaran
Fix the channel_index table layout to fetch the correct channel_index when calculating physical address from normalized address during page retirement. Also, fix the number of UMC instances and number of channels within each UMC instance for Aldebaran. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-By: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1171,8 +1171,8 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
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break;
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case CHIP_ALDEBARAN:
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adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM;
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adev->umc.channel_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
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adev->umc.umc_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
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adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
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adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
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adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
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if (!adev->gmc.xgmi.connected_to_cpu)
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adev->umc.ras_funcs = &umc_v6_7_ras_funcs;
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@ -30,17 +30,17 @@
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const uint32_t
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umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {
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{28, 12, 6, 22}, {19, 3, 9, 25},
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{20, 4, 30, 14}, {11, 27, 1, 17},
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{24, 8, 2, 18}, {15, 31, 5, 21},
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{16, 0, 26, 10}, {7, 23, 29, 13}
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{28, 20, 24, 16, 12, 4, 8, 0},
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{6, 30, 2, 26, 22, 14, 18, 10},
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{19, 11, 15, 7, 3, 27, 31, 23},
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{9, 1, 5, 29, 25, 17, 21, 13}
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};
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const uint32_t
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umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {
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{19, 3, 9, 25}, {28, 12, 6, 22},
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{11, 27, 1, 17}, {20, 4, 30, 14},
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{15, 31, 5, 21}, {24, 8, 2, 18},
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{7, 23, 29, 13}, {16, 0, 26, 10}
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{19, 11, 15, 7, 3, 27, 31, 23},
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{9, 1, 5, 29, 25, 17, 21, 13},
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{28, 20, 24, 16, 12, 4, 8, 0},
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{6, 30, 2, 26, 22, 14, 18, 10},
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};
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static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev,
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@ -36,9 +36,9 @@
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#define UMC_V6_7_INST_DIST 0x40000
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/* number of umc channel instance with memory map register access */
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#define UMC_V6_7_CHANNEL_INSTANCE_NUM 4
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#define UMC_V6_7_UMC_INSTANCE_NUM 4
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/* number of umc instance with memory map register access */
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#define UMC_V6_7_UMC_INSTANCE_NUM 8
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#define UMC_V6_7_CHANNEL_INSTANCE_NUM 8
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/* total channel instances in one umc block */
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#define UMC_V6_7_TOTAL_CHANNEL_NUM (UMC_V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)
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/* UMC regiser per channel offset */
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