drm/amdgpu: Add umc v12_0 ras functions
Add umc v12_0 ras error querying. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Candice Li
Alex Deucher
@ -118,7 +118,7 @@ amdgpu-y += \
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# add UMC block
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amdgpu-y += \
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umc_v6_0.o umc_v6_1.o umc_v6_7.o umc_v8_7.o umc_v8_10.o
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umc_v6_0.o umc_v6_1.o umc_v6_7.o umc_v8_7.o umc_v8_10.o umc_v12_0.o
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# add IH block
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amdgpu-y += \
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@ -56,6 +56,7 @@
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#include "umc_v6_1.h"
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#include "umc_v6_0.h"
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#include "umc_v6_7.h"
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#include "umc_v12_0.h"
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#include "hdp_v4_0.h"
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#include "mca_v3_0.h"
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@ -735,7 +736,8 @@ static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
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adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
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if (!amdgpu_sriov_vf(adev) &&
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!adev->gmc.xgmi.connected_to_cpu) {
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!adev->gmc.xgmi.connected_to_cpu &&
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!adev->gmc.is_app_apu) {
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adev->gmc.ecc_irq.num_types = 1;
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adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
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}
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@ -1490,6 +1492,16 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
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else
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adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
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break;
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case IP_VERSION(12, 0, 0):
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adev->umc.max_ras_err_cnt_per_query = UMC_V12_0_TOTAL_CHANNEL_NUM(adev);
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adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM;
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adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM;
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adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM;
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adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET;
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adev->umc.active_mask = adev->aid_mask;
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if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
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adev->umc.ras = &umc_v12_0_ras;
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break;
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default:
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break;
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}
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@ -2141,7 +2153,8 @@ static int gmc_v9_0_sw_init(void *handle)
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return r;
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if (!amdgpu_sriov_vf(adev) &&
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!adev->gmc.xgmi.connected_to_cpu) {
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!adev->gmc.xgmi.connected_to_cpu &&
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!adev->gmc.is_app_apu) {
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/* interrupt sent to DF. */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
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&adev->gmc.ecc_irq);
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256
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
Normal file
256
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
Normal file
@ -0,0 +1,256 @@
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "umc_v12_0.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_umc.h"
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#include "amdgpu.h"
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#include "umc/umc_12_0_0_offset.h"
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#include "umc/umc_12_0_0_sh_mask.h"
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static inline uint64_t get_umc_v12_0_reg_offset(struct amdgpu_device *adev,
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uint32_t node_inst,
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uint32_t umc_inst,
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uint32_t ch_inst)
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{
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uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst;
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uint64_t cross_node_offset = (node_inst == 0) ? 0 : UMC_V12_0_CROSS_NODE_OFFSET;
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umc_inst = index / 4;
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ch_inst = index % 4;
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return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST * umc_inst +
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UMC_V12_0_NODE_DIST * node_inst + cross_node_offset;
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}
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static int umc_v12_0_reset_error_count_per_channel(struct amdgpu_device *adev,
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uint32_t node_inst, uint32_t umc_inst,
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uint32_t ch_inst, void *data)
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{
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uint64_t odecc_err_cnt_addr;
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uint64_t umc_reg_offset =
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get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst);
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odecc_err_cnt_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt);
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/* clear error count */
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WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4,
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UMC_V12_0_CE_CNT_INIT);
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return 0;
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}
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static void umc_v12_0_reset_error_count(struct amdgpu_device *adev)
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{
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amdgpu_umc_loop_channels(adev,
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umc_v12_0_reset_error_count_per_channel, NULL);
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}
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static void umc_v12_0_query_correctable_error_count(struct amdgpu_device *adev,
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uint64_t umc_reg_offset,
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unsigned long *error_count)
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{
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uint64_t mc_umc_status;
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uint64_t mc_umc_status_addr;
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mc_umc_status_addr =
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SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
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/* Rely on MCUMC_STATUS for correctable error counter
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* MCUMC_STATUS is a 64 bit register
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*/
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mc_umc_status =
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RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4);
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if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
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*error_count += 1;
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}
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static void umc_v12_0_query_uncorrectable_error_count(struct amdgpu_device *adev,
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uint64_t umc_reg_offset,
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unsigned long *error_count)
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{
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uint64_t mc_umc_status;
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uint64_t mc_umc_status_addr;
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mc_umc_status_addr =
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SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
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/* Check the MCUMC_STATUS. */
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mc_umc_status =
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RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4);
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if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
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(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
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*error_count += 1;
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}
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static int umc_v12_0_query_error_count(struct amdgpu_device *adev,
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uint32_t node_inst, uint32_t umc_inst,
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uint32_t ch_inst, void *data)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)data;
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uint64_t umc_reg_offset =
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get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst);
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umc_v12_0_query_correctable_error_count(adev,
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umc_reg_offset,
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&(err_data->ce_count));
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umc_v12_0_query_uncorrectable_error_count(adev,
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umc_reg_offset,
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&(err_data->ue_count));
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return 0;
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}
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static void umc_v12_0_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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amdgpu_umc_loop_channels(adev,
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umc_v12_0_query_error_count, ras_error_status);
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umc_v12_0_reset_error_count(adev);
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}
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static void umc_v12_0_convert_error_address(struct amdgpu_device *adev,
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struct ras_err_data *err_data, uint64_t err_addr,
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uint32_t ch_inst, uint32_t umc_inst,
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uint32_t node_inst)
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{
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}
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static int umc_v12_0_query_error_address(struct amdgpu_device *adev,
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uint32_t node_inst, uint32_t umc_inst,
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uint32_t ch_inst, void *data)
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{
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uint64_t mc_umc_status_addr;
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uint64_t mc_umc_status, err_addr;
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uint64_t mc_umc_addrt0;
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struct ras_err_data *err_data = (struct ras_err_data *)data;
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uint64_t umc_reg_offset =
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get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst);
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mc_umc_status_addr =
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SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
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mc_umc_status = RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4);
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if (mc_umc_status == 0)
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return 0;
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if (!err_data->err_addr) {
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/* clear umc status */
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WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
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return 0;
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}
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/* calculate error address if ue error is detected */
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if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
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mc_umc_addrt0 =
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SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
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err_addr = RREG64_PCIE_EXT((mc_umc_addrt0 + umc_reg_offset) * 4);
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err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
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umc_v12_0_convert_error_address(adev, err_data, err_addr,
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ch_inst, umc_inst, node_inst);
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}
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/* clear umc status */
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WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
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return 0;
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}
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static void umc_v12_0_query_ras_error_address(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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amdgpu_umc_loop_channels(adev,
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umc_v12_0_query_error_address, ras_error_status);
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}
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static int umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev,
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uint32_t node_inst, uint32_t umc_inst,
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uint32_t ch_inst, void *data)
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{
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uint32_t odecc_cnt_sel;
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uint64_t odecc_cnt_sel_addr, odecc_err_cnt_addr;
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uint64_t umc_reg_offset =
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get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst);
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odecc_cnt_sel_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccCntSel);
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odecc_err_cnt_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt);
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odecc_cnt_sel = RREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4);
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/* set ce error interrupt type to APIC based interrupt */
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odecc_cnt_sel = REG_SET_FIELD(odecc_cnt_sel, UMCCH0_OdEccCntSel,
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OdEccErrInt, 0x1);
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WREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4, odecc_cnt_sel);
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/* set error count to initial value */
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WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V12_0_CE_CNT_INIT);
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return 0;
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}
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static void umc_v12_0_err_cnt_init(struct amdgpu_device *adev)
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{
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amdgpu_umc_loop_channels(adev,
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umc_v12_0_err_cnt_init_per_channel, NULL);
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}
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static bool umc_v12_0_query_ras_poison_mode(struct amdgpu_device *adev)
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{
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/*
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* Force return true, because regUMCCH0_EccCtrl
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* is not accessible from host side
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*/
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return true;
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}
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const struct amdgpu_ras_block_hw_ops umc_v12_0_ras_hw_ops = {
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.query_ras_error_count = umc_v12_0_query_ras_error_count,
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.query_ras_error_address = umc_v12_0_query_ras_error_address,
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};
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struct amdgpu_umc_ras umc_v12_0_ras = {
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.ras_block = {
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.hw_ops = &umc_v12_0_ras_hw_ops,
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},
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.err_cnt_init = umc_v12_0_err_cnt_init,
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.query_ras_poison_mode = umc_v12_0_query_ras_poison_mode,
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};
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56
drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
Normal file
56
drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
Normal file
@ -0,0 +1,56 @@
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __UMC_V12_0_H__
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#define __UMC_V12_0_H__
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#include "soc15_common.h"
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#include "amdgpu.h"
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#define UMC_V12_0_NODE_DIST 0x40000000
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#define UMC_V12_0_INST_DIST 0x40000
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/* UMC register per channel offset */
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#define UMC_V12_0_PER_CHANNEL_OFFSET 0x400
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/* UMC cross node offset */
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#define UMC_V12_0_CROSS_NODE_OFFSET 0x100000000
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/* OdEccErrCnt max value */
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#define UMC_V12_0_CE_CNT_MAX 0xffff
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/* umc ce interrupt threshold */
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#define UMC_V12_0_CE_INT_THRESHOLD 0xffff
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/* umc ce count initial value */
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#define UMC_V12_0_CE_CNT_INIT (UMC_V12_0_CE_CNT_MAX - UMC_V12_0_CE_INT_THRESHOLD)
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/* number of umc channel instance with memory map register access */
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#define UMC_V12_0_CHANNEL_INSTANCE_NUM 8
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/* number of umc instance with memory map register access */
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#define UMC_V12_0_UMC_INSTANCE_NUM 4
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/* Total channel instances for all available umc nodes */
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#define UMC_V12_0_TOTAL_CHANNEL_NUM(adev) \
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(UMC_V12_0_CHANNEL_INSTANCE_NUM * (adev)->gmc.num_umc)
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extern struct amdgpu_umc_ras umc_v12_0_ras;
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#endif
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