mlxsw: reg: Mark SFGC & some SFMR fields as reserved in CFF mode
Some existing fields and the whole register of SFGC are reserved in CFF mode. Backport the reservation note to these fields. Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Link: https://lore.kernel.org/r/e1d5977a8cb778227e4ea2fd1515529957ce5de7.1700503643.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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@ -1024,6 +1024,8 @@ static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port,
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* ------------------------------------------
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* The following register controls the association of flooding tables and MIDs
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* to packet types used for flooding.
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*
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* Reserved when CONFIG_PROFILE.flood_mode = CFF.
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*/
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#define MLXSW_REG_SFGC_ID 0x2011
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#define MLXSW_REG_SFGC_LEN 0x14
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@ -1862,6 +1864,7 @@ MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
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* Access: RW
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*
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* Note: Reserved when legacy bridge model is used.
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* Reserved when CONFIG_PROFILE.flood_mode = CFF.
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*/
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MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1);
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@ -1872,6 +1875,7 @@ MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1);
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* Access: RW
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*
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* Note: Reserved when legacy bridge model is used and when flood_rsp=1.
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* Reserved when CONFIG_PROFILE.flood_mode = CFF
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*/
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MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1);
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@ -1880,6 +1884,8 @@ MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1);
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* Used to point into the flooding table selected by SFGC register if
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* the table is of type FID-Offset. Otherwise, this field is reserved.
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* Access: RW
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*
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* Note: Reserved when CONFIG_PROFILE.flood_mode = CFF
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*/
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MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
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