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MIPS: CPC: Use BIT/GENMASK for register fields, order & drop shifts

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Tidy up asm/mips-cpc.h in a similar way to what "MIPS: CM: Use
BIT/GENMASK for register fields, order & drop shifts" did for
asm/mips-cm.h.

We use BIT() & GENMASK() to simplify the definition of register fields,
drop the _SHF definitions since that information can be found in the
_MSK ones, and then drop the _MSK suffix.

Fields definitions are moved to be next to the appropriate register
definition, making it easier to link the two & keep everything ordered
by register address. Comments are added including the name of each
register & a brief description of its purpose which helps to understand
what registers are for, link them back to hardware documentation or grep
for them.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17003/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton 2017-08-12 19:49:29 -07:00 committed by Ralf Baechle
parent 2c981e325f
commit 829ca2be9c
4 changed files with 49 additions and 42 deletions
arch/mips
include/asm
mips-cpc.h
kernel
mips-cpc.cpm-cps.csmp-cps.c

79
arch/mips/include/asm/mips-cpc.h

@ -76,56 +76,61 @@ static inline bool mips_cpc_present(void)
CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name) \
CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
/* GCB register accessor functions */
/* CPC_ACCESS - Control core/IOCU access to CPC registers prior to CM 3 */
CPC_ACCESSOR_RW(32, 0x000, access)
/* CPC_SEQDEL - Configure delays between command sequencer steps */
CPC_ACCESSOR_RW(32, 0x008, seqdel)
/* CPC_RAIL - Configure the delay from rail power-up to stability */
CPC_ACCESSOR_RW(32, 0x010, rail)
/* CPC_RESETLEN - Configure the length of reset sequences */
CPC_ACCESSOR_RW(32, 0x018, resetlen)
/* CPC_REVISION - Indicates the revisison of the CPC */
CPC_ACCESSOR_RO(32, 0x020, revision)
/* Core Local & Core Other accessor functions */
/* CPC_Cx_CMD - Instruct the CPC to take action on a core */
CPC_CX_ACCESSOR_RW(32, 0x000, cmd)
#define CPC_Cx_CMD GENMASK(3, 0)
#define CPC_Cx_CMD_CLOCKOFF 0x1
#define CPC_Cx_CMD_PWRDOWN 0x2
#define CPC_Cx_CMD_PWRUP 0x3
#define CPC_Cx_CMD_RESET 0x4
/* CPC_Cx_STAT_CONF - Indicates core configuration & state */
CPC_CX_ACCESSOR_RW(32, 0x008, stat_conf)
#define CPC_Cx_STAT_CONF_PWRUPE BIT(23)
#define CPC_Cx_STAT_CONF_SEQSTATE GENMASK(22, 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_D0 0x0
#define CPC_Cx_STAT_CONF_SEQSTATE_U0 0x1
#define CPC_Cx_STAT_CONF_SEQSTATE_U1 0x2
#define CPC_Cx_STAT_CONF_SEQSTATE_U2 0x3
#define CPC_Cx_STAT_CONF_SEQSTATE_U3 0x4
#define CPC_Cx_STAT_CONF_SEQSTATE_U4 0x5
#define CPC_Cx_STAT_CONF_SEQSTATE_U5 0x6
#define CPC_Cx_STAT_CONF_SEQSTATE_U6 0x7
#define CPC_Cx_STAT_CONF_SEQSTATE_D1 0x8
#define CPC_Cx_STAT_CONF_SEQSTATE_D3 0x9
#define CPC_Cx_STAT_CONF_SEQSTATE_D2 0xa
#define CPC_Cx_STAT_CONF_CLKGAT_IMPL BIT(17)
#define CPC_Cx_STAT_CONF_PWRDN_IMPL BIT(16)
#define CPC_Cx_STAT_CONF_EJTAG_PROBE BIT(15)
/* CPC_Cx_OTHER - Configure the core-other register block prior to CM 3 */
CPC_CX_ACCESSOR_RW(32, 0x010, other)
#define CPC_Cx_OTHER_CORENUM GENMASK(23, 16)
/* CPC_Cx_VP_STOP - Stop Virtual Processors (VPs) within a core from running */
CPC_CX_ACCESSOR_RW(32, 0x020, vp_stop)
/* CPC_Cx_VP_START - Start Virtual Processors (VPs) within a core running */
CPC_CX_ACCESSOR_RW(32, 0x028, vp_run)
/* CPC_Cx_VP_RUNNING - Indicate which Virtual Processors (VPs) are running */
CPC_CX_ACCESSOR_RW(32, 0x030, vp_running)
/* CPC_Cx_CMD register fields */
#define CPC_Cx_CMD_SHF 0
#define CPC_Cx_CMD_MSK (_ULCAST_(0xf) << 0)
#define CPC_Cx_CMD_CLOCKOFF (_ULCAST_(0x1) << 0)
#define CPC_Cx_CMD_PWRDOWN (_ULCAST_(0x2) << 0)
#define CPC_Cx_CMD_PWRUP (_ULCAST_(0x3) << 0)
#define CPC_Cx_CMD_RESET (_ULCAST_(0x4) << 0)
/* CPC_Cx_STAT_CONF register fields */
#define CPC_Cx_STAT_CONF_PWRUPE_SHF 23
#define CPC_Cx_STAT_CONF_PWRUPE_MSK (_ULCAST_(0x1) << 23)
#define CPC_Cx_STAT_CONF_SEQSTATE_SHF 19
#define CPC_Cx_STAT_CONF_SEQSTATE_MSK (_ULCAST_(0xf) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_D0 (_ULCAST_(0x0) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U0 (_ULCAST_(0x1) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U1 (_ULCAST_(0x2) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U2 (_ULCAST_(0x3) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U3 (_ULCAST_(0x4) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U4 (_ULCAST_(0x5) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U5 (_ULCAST_(0x6) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U6 (_ULCAST_(0x7) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_D1 (_ULCAST_(0x8) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_D3 (_ULCAST_(0x9) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_D2 (_ULCAST_(0xa) << 19)
#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_SHF 17
#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK (_ULCAST_(0x1) << 17)
#define CPC_Cx_STAT_CONF_PWRDN_IMPL_SHF 16
#define CPC_Cx_STAT_CONF_PWRDN_IMPL_MSK (_ULCAST_(0x1) << 16)
#define CPC_Cx_STAT_CONF_EJTAG_PROBE_SHF 15
#define CPC_Cx_STAT_CONF_EJTAG_PROBE_MSK (_ULCAST_(0x1) << 15)
/* CPC_Cx_OTHER register fields */
#define CPC_Cx_OTHER_CORENUM_SHF 16
#define CPC_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xff) << 16)
#ifdef CONFIG_MIPS_CPC
/**

2
arch/mips/kernel/mips-cpc.c

@ -89,7 +89,7 @@ void mips_cpc_lock_other(unsigned int core)
curr_core = current_cpu_data.core;
spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
per_cpu(cpc_core_lock_flags, curr_core));
write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF);
write_cpc_cl_other(core << __ffs(CPC_Cx_OTHER_CORENUM));
/*
* Ensure the core-other region reflects the appropriate core &

2
arch/mips/kernel/pm-cps.c

@ -692,7 +692,7 @@ static int __init cps_pm_init(void)
/* Detect whether a CPC is present */
if (mips_cpc_present()) {
/* Detect whether clock gating is implemented */
if (read_cpc_cl_stat_conf() & CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK)
if (read_cpc_cl_stat_conf() & CPC_Cx_STAT_CONF_CLKGAT_IMPL)
set_bit(CPS_PM_CLOCK_GATED, state_support);
else
pr_warn("pm-cps: CPC does not support clock gating\n");

8
arch/mips/kernel/smp-cps.c

@ -253,7 +253,8 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
timeout = 100;
while (true) {
stat = read_cpc_co_stat_conf();
seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE_MSK;
seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
/* U6 == coherent execution, ie. the core is up */
if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
@ -522,7 +523,8 @@ static void cps_cpu_die(unsigned int cpu)
mips_cm_lock_other(core, 0);
mips_cpc_lock_other(core);
stat = read_cpc_co_stat_conf();
stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
stat &= CPC_Cx_STAT_CONF_SEQSTATE;
stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
mips_cpc_unlock_other();
mips_cm_unlock_other();
@ -544,7 +546,7 @@ static void cps_cpu_die(unsigned int cpu)
*/
if (WARN(ktime_after(ktime_get(), fail_time),
"CPU%u hasn't powered down, seq. state %u\n",
cpu, stat >> CPC_Cx_STAT_CONF_SEQSTATE_SHF))
cpu, stat))
break;
} while (1);