Power management fixes for 6.5-rc3
Revert three recent intel_idle commits that introduced a functional issue, included a coding mistake and have been questioned at the design level. -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEE4fcc61cGeeHD/fCwgsRv/nhiVHEFAmS6psISHHJqd0Byand5 c29ja2kubmV0AAoJEILEb/54YlRx79sP/1h7M/EjphvOD26SRe9SOlV1bd84Satt +eCMVaDHoshdhK5lHPUvR6fm9STh2BWV9IOuvSiKVaCYe5W6Kg+SW4ffJVOx53AR oyqS4ukgenc8c4HswsPx1B27rjvX2rxXDcz88civhPjKNYuTeZhTvoeyZg8ooWRP ulFOrdvHUOAKhGOV1PNgjpUlIIl6/OwzaowCiRswUhN2uKDeAkIt0a3JLSGPAHnr XvruaaQcQda81PHEWylShbyOsVmAKNO1xq2mjQwd18LE0TOLVMMKPjMrisGkQK76 1995NNExcsqvSC6LiJKWA1BEfNp4zWs12aApBuJg08JLGcpuW8SAz/pPyFXpDWHF QY6Io1Ph5+f4k/V5i8CM2ZkYVUBiJ/3sPOAgJqsVhIyBeoEhUifYfH8rdNOMFqq5 7tUoqAZ/H8catl+zHMG5qttkLMQlVT3JsrRiJdWFV7ThwZtqVUaJ9tUUKVMqKKrF O80EKLK2bFn1fMnJgkebYUcWqa2pAuRqFHW/Rs37QLfu40N0yznQsWCq7ND3IxRx sIc8t9aFSI20UJ7ju+TwDr3+qrQ9rzhPHINcrn0e861Qa2svcu9NN99QUB3MYrz1 M0upWsRTpYaTJUsESfR7OSvIcHo/b+6pDmo750rAGF9VwRbgEZxZu6/gr5mYMHkR qcwwB149gUIu =90UR -----END PGP SIGNATURE----- Merge tag 'pm-6.5-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull power management fixes from Rafael Wysocki: "Revert three recent intel_idle commits that introduced a functional issue, included a coding mistake and have been questioned at the design level" * tag 'pm-6.5-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: Revert "intel_idle: Add support for using intel_idle in a VM guest using just hlt" Revert "intel_idle: Add a "Long HLT" C1 state for the VM guest mode" Revert "intel_idle: Add __init annotation to matchup_vm_state_with_baremetal()"
This commit is contained in:
Linus Torvalds
commit
892d7c1b29
@ -199,43 +199,6 @@ static __cpuidle int intel_idle_xstate(struct cpuidle_device *dev,
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return __intel_idle(dev, drv, index);
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}
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static __always_inline int __intel_idle_hlt(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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raw_safe_halt();
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raw_local_irq_disable();
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return index;
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}
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/**
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* intel_idle_hlt - Ask the processor to enter the given idle state using hlt.
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* @dev: cpuidle device of the target CPU.
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* @drv: cpuidle driver (assumed to point to intel_idle_driver).
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* @index: Target idle state index.
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*
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* Use the HLT instruction to notify the processor that the CPU represented by
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* @dev is idle and it can try to enter the idle state corresponding to @index.
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*
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* Must be called under local_irq_disable().
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*/
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static __cpuidle int intel_idle_hlt(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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return __intel_idle_hlt(dev, drv, index);
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}
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static __cpuidle int intel_idle_hlt_irq_on(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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int ret;
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raw_local_irq_enable();
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ret = __intel_idle_hlt(dev, drv, index);
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raw_local_irq_disable();
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return ret;
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}
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/**
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* intel_idle_s2idle - Ask the processor to enter the given idle state.
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* @dev: cpuidle device of the target CPU.
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@ -1279,25 +1242,6 @@ static struct cpuidle_state snr_cstates[] __initdata = {
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.enter = NULL }
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};
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static struct cpuidle_state vmguest_cstates[] __initdata = {
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{
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.name = "C1",
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.desc = "HLT",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE,
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.exit_latency = 5,
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.target_residency = 10,
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.enter = &intel_idle_hlt, },
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{
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.name = "C1L",
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.desc = "Long HLT",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 5,
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.target_residency = 200,
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.enter = &intel_idle_hlt, },
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{
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.enter = NULL }
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};
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static const struct idle_cpu idle_cpu_nehalem __initconst = {
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.state_table = nehalem_cstates,
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.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
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@ -1897,16 +1841,6 @@ static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
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static void state_update_enter_method(struct cpuidle_state *state, int cstate)
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{
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if (state->enter == intel_idle_hlt) {
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if (force_irq_on) {
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pr_info("forced intel_idle_irq for state %d\n", cstate);
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state->enter = intel_idle_hlt_irq_on;
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}
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return;
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}
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if (state->enter == intel_idle_hlt_irq_on)
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return; /* no update scenarios */
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if (state->flags & CPUIDLE_FLAG_INIT_XSTATE) {
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/*
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* Combining with XSTATE with IBRS or IRQ_ENABLE flags
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@ -1940,21 +1874,6 @@ static void state_update_enter_method(struct cpuidle_state *state, int cstate)
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}
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}
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/*
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* For mwait based states, we want to verify the cpuid data to see if the state
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* is actually supported by this specific CPU.
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* For non-mwait based states, this check should be skipped.
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*/
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static bool should_verify_mwait(struct cpuidle_state *state)
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{
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if (state->enter == intel_idle_hlt)
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return false;
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if (state->enter == intel_idle_hlt_irq_on)
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return false;
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return true;
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}
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static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
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{
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int cstate;
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@ -2003,7 +1922,7 @@ static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
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}
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mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
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if (should_verify_mwait(&cpuidle_state_table[cstate]) && !intel_idle_verify_cstate(mwait_hint))
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if (!intel_idle_verify_cstate(mwait_hint))
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continue;
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/* Structure copy. */
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@ -2137,93 +2056,6 @@ static void __init intel_idle_cpuidle_devices_uninit(void)
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cpuidle_unregister_device(per_cpu_ptr(intel_idle_cpuidle_devices, i));
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}
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/*
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* Match up the latency and break even point of the bare metal (cpu based)
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* states with the deepest VM available state.
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*
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* We only want to do this for the deepest state, the ones that has
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* the TLB_FLUSHED flag set on the .
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*
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* All our short idle states are dominated by vmexit/vmenter latencies,
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* not the underlying hardware latencies so we keep our values for these.
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*/
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static void __init matchup_vm_state_with_baremetal(void)
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{
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int cstate;
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for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
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int matching_cstate;
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if (intel_idle_max_cstate_reached(cstate))
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break;
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if (!cpuidle_state_table[cstate].enter)
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break;
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if (!(cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_TLB_FLUSHED))
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continue;
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for (matching_cstate = 0; matching_cstate < CPUIDLE_STATE_MAX; ++matching_cstate) {
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if (!icpu->state_table[matching_cstate].enter)
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break;
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if (icpu->state_table[matching_cstate].exit_latency > cpuidle_state_table[cstate].exit_latency) {
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cpuidle_state_table[cstate].exit_latency = icpu->state_table[matching_cstate].exit_latency;
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cpuidle_state_table[cstate].target_residency = icpu->state_table[matching_cstate].target_residency;
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}
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}
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}
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}
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static int __init intel_idle_vminit(const struct x86_cpu_id *id)
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{
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int retval;
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cpuidle_state_table = vmguest_cstates;
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icpu = (const struct idle_cpu *)id->driver_data;
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pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n",
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boot_cpu_data.x86_model);
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intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
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if (!intel_idle_cpuidle_devices)
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return -ENOMEM;
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/*
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* We don't know exactly what the host will do when we go idle, but as a worst estimate
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* we can assume that the exit latency of the deepest host state will be hit for our
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* deep (long duration) guest idle state.
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* The same logic applies to the break even point for the long duration guest idle state.
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* So lets copy these two properties from the table we found for the host CPU type.
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*/
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matchup_vm_state_with_baremetal();
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intel_idle_cpuidle_driver_init(&intel_idle_driver);
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retval = cpuidle_register_driver(&intel_idle_driver);
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if (retval) {
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struct cpuidle_driver *drv = cpuidle_get_driver();
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printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"),
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drv ? drv->name : "none");
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goto init_driver_fail;
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}
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retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online",
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intel_idle_cpu_online, NULL);
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if (retval < 0)
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goto hp_setup_fail;
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return 0;
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hp_setup_fail:
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intel_idle_cpuidle_devices_uninit();
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cpuidle_unregister_driver(&intel_idle_driver);
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init_driver_fail:
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free_percpu(intel_idle_cpuidle_devices);
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return retval;
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}
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static int __init intel_idle_init(void)
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{
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const struct x86_cpu_id *id;
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@ -2242,8 +2074,6 @@ static int __init intel_idle_init(void)
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id = x86_match_cpu(intel_idle_ids);
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if (id) {
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if (!boot_cpu_has(X86_FEATURE_MWAIT)) {
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if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
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return intel_idle_vminit(id);
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pr_debug("Please enable MWAIT in BIOS SETUP\n");
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return -ENODEV;
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}
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