iommu/amd: Reserve exclusion range in iova-domain
If a device has an exclusion range specified in the IVRS
table, this region needs to be reserved in the iova-domain
of that device. This hasn't happened until now and can cause
data corruption on data transfered with these devices.
Treat exclusion ranges as reserved regions in the iommu-core
to fix the problem.
Fixes: be2a022c0d
('x86, AMD IOMMU: add functions to parse IOMMU memory mapping requirements for devices')
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Reviewed-by: Gary R Hook <gary.hook@amd.com>
This commit is contained in:
parent
8bc32a2856
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8aafaaf221
@ -3169,21 +3169,24 @@ static void amd_iommu_get_resv_regions(struct device *dev,
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return;
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list_for_each_entry(entry, &amd_iommu_unity_map, list) {
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int type, prot = 0;
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size_t length;
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int prot = 0;
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if (devid < entry->devid_start || devid > entry->devid_end)
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continue;
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type = IOMMU_RESV_DIRECT;
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length = entry->address_end - entry->address_start;
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if (entry->prot & IOMMU_PROT_IR)
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prot |= IOMMU_READ;
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if (entry->prot & IOMMU_PROT_IW)
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prot |= IOMMU_WRITE;
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if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
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/* Exclusion range */
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type = IOMMU_RESV_RESERVED;
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region = iommu_alloc_resv_region(entry->address_start,
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length, prot,
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IOMMU_RESV_DIRECT);
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length, prot, type);
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if (!region) {
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dev_err(dev, "Out of memory allocating dm-regions\n");
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return;
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@ -2013,6 +2013,9 @@ static int __init init_unity_map_range(struct ivmd_header *m)
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if (e == NULL)
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return -ENOMEM;
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if (m->flags & IVMD_FLAG_EXCL_RANGE)
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init_exclusion_range(m);
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switch (m->type) {
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default:
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kfree(e);
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@ -2059,9 +2062,7 @@ static int __init init_memory_definitions(struct acpi_table_header *table)
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while (p < end) {
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m = (struct ivmd_header *)p;
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if (m->flags & IVMD_FLAG_EXCL_RANGE)
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init_exclusion_range(m);
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else if (m->flags & IVMD_FLAG_UNITY_MAP)
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if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE))
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init_unity_map_range(m);
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p += m->length;
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@ -374,6 +374,8 @@
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#define IOMMU_PROT_IR 0x01
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#define IOMMU_PROT_IW 0x02
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#define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2)
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/* IOMMU capabilities */
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#define IOMMU_CAP_IOTLB 24
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#define IOMMU_CAP_NPCACHE 26
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