Revert "ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U"
This reverts commit 3d2d52a0d1835b56f6bd67d268f6c39df0e41692, it caused a build regression: arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:109.4-14: Warning (reg_format): /switch/ports:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #address-cells value arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #size-cells value Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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d8db5d8a01
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@ -93,83 +93,6 @@
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gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
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};
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};
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switch {
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compatible = "realtek,rtl8365mb";
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/* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */
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mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
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mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
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realtek,disable-leds;
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dsa,member = <1 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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port@0 {
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reg = <0>;
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label = "lan5";
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phy-handle = <ðphy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan6";
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phy-handle = <ðphy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan7";
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phy-handle = <ðphy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan8";
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phy-handle = <ðphy3>;
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&sw0_p5>;
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phy-mode = "rgmii";
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tx-internal-delay-ps = <2000>;
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rx-internal-delay-ps = <2100>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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mdio {
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compatible = "realtek,smi-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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};
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ethphy2: ethernet-phy@2 {
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reg = <2>;
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};
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ethphy3: ethernet-phy@3 {
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reg = <3>;
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};
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};
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};
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};
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&srab {
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