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staging: rtl8192e: Join constants Rtl819XPHY_REG_.. with ..PciEPHY_REG_..

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Join constants Rtl819XPHY_REG_1T2RArray with Rtl8192PciEPHY_REG_1T2RArray
to RTL8192E_PHY_REG_1T2R_ARR to improve readability.

Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/2816a10a8a534014c58e0092b78443e01a67930a.1678814935.git.philipp.g.hortmann@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Philipp Hortmann 2023-03-14 19:44:20 +01:00 committed by Greg Kroah-Hartman
parent dc756b9354
commit 94f7d4a464
4 changed files with 3 additions and 5 deletions
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2
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c
View File

@ -316,7 +316,7 @@ static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType)
Rtl819XAGCTAB_Array_Table = RTL8192E_AGCTAB_ARR;
if (priv->rf_type == RF_1T2R) {
PHY_REGArrayLen = RTL8192E_PHY_REG_1T2R_ARR_LEN;
Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
Rtl819XPHY_REGArray_Table = RTL8192E_PHY_REG_1T2R_ARR;
}
if (ConfigType == BB_CONFIG_PHY_REG) {

2
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h
View File

@ -9,8 +9,6 @@
#define MAX_DOZE_WAITING_TIMES_9x 64
#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
extern u32 rtl819XAGCTAB_Array[];
enum hw90_block {

2
drivers/staging/rtl8192e/rtl8192e/table.c
View File

@ -6,7 +6,7 @@
*/
#include "table.h"
u32 Rtl8192PciEPHY_REG_1T2RArray[RTL8192E_PHY_REG_1T2R_ARR_LEN] = {
u32 RTL8192E_PHY_REG_1T2R_ARR[RTL8192E_PHY_REG_1T2R_ARR_LEN] = {
0x800, 0x00000000,
0x804, 0x00000001,
0x808, 0x0000fc00,

2
drivers/staging/rtl8192e/rtl8192e/table.h
View File

@ -12,7 +12,7 @@
#include <linux/types.h>
#define RTL8192E_PHY_REG_1T2R_ARR_LEN 296
extern u32 Rtl8192PciEPHY_REG_1T2RArray[RTL8192E_PHY_REG_1T2R_ARR_LEN];
extern u32 RTL8192E_PHY_REG_1T2R_ARR[RTL8192E_PHY_REG_1T2R_ARR_LEN];
#define RTL8192E_RADIO_A_ARR_LEN 246
extern u32 RTL8192E_RADIO_A_ARR[RTL8192E_RADIO_A_ARR_LEN];
#define RTL8192E_RADIO_B_ARR_LEN 78