drm/amd/display: Program plane color setting correctly
[why] There are some registers for plane color that are skipped programming on resume. Need to add those as part of the sequence. [how] Add new function hook for programming plane color control. Reviewed-by: Duncan Ma <duncan.ma@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sung Joon Kim
Alex Deucher
parent
23618280cc
commit
995dedb7a4
@ -316,7 +316,7 @@ bool hubp3_program_surface_flip_and_addr(
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return true;
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}
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static void hubp3_program_tiling(
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void hubp3_program_tiling(
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struct dcn20_hubp *hubp2,
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const union dc_tiling_info *info,
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const enum surface_pixel_format pixel_format)
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@ -278,6 +278,11 @@ void hubp3_setup(
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struct _vcs_dpi_display_rq_regs_st *rq_regs,
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struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
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void hubp3_program_tiling(
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struct dcn20_hubp *hubp2,
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const union dc_tiling_info *info,
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const enum surface_pixel_format pixel_format);
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void hubp3_dcc_control(struct hubp *hubp, bool enable,
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enum hubp_ind_block_size blk_size);
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@ -53,11 +53,146 @@ static void hubp35_init(struct hubp *hubp)
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/*do nothing for now for dcn3.5 or later*/
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}
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void hubp35_program_pixel_format(
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struct hubp *hubp,
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enum surface_pixel_format format)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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uint32_t green_bar = 1;
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uint32_t red_bar = 3;
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uint32_t blue_bar = 2;
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/* swap for ABGR format */
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if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
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|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
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|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
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|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
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|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
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red_bar = 2;
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blue_bar = 3;
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}
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REG_UPDATE_3(HUBPRET_CONTROL,
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CROSSBAR_SRC_Y_G, green_bar,
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CROSSBAR_SRC_CB_B, blue_bar,
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CROSSBAR_SRC_CR_R, red_bar);
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/* Mapping is same as ipp programming (cnvc) */
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switch (format) {
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 1);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 3);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 8);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 10);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /* we use crossbar already */
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 24);
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 65);
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 64);
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 67);
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 66);
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 12);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 112);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 113);
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 114);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 118);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 119);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
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REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 116,
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ALPHA_PLANE_EN, 0);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
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REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 116,
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ALPHA_PLANE_EN, 1);
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break;
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default:
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BREAK_TO_DEBUGGER();
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break;
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}
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/* don't see the need of program the xbar in DCN 1.0 */
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}
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void hubp35_program_surface_config(
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struct hubp *hubp,
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enum surface_pixel_format format,
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union dc_tiling_info *tiling_info,
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struct plane_size *plane_size,
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enum dc_rotation_angle rotation,
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struct dc_plane_dcc_param *dcc,
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bool horizontal_mirror,
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unsigned int compat_level)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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hubp3_dcc_control_sienna_cichlid(hubp, dcc);
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hubp3_program_tiling(hubp2, tiling_info, format);
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hubp2_program_size(hubp, format, plane_size, dcc);
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hubp2_program_rotation(hubp, rotation, horizontal_mirror);
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hubp35_program_pixel_format(hubp, format);
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}
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struct hubp_funcs dcn35_hubp_funcs = {
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.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
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.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
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.hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
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.hubp_program_surface_config = hubp3_program_surface_config,
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.hubp_program_surface_config = hubp35_program_surface_config,
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.hubp_is_flip_pending = hubp2_is_flip_pending,
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.hubp_setup = hubp3_setup,
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.hubp_setup_interdependent = hubp2_setup_interdependent,
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@ -58,4 +58,18 @@ bool hubp35_construct(
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void hubp35_set_fgcg(struct hubp *hubp, bool enable);
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void hubp35_program_pixel_format(
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struct hubp *hubp,
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enum surface_pixel_format format);
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void hubp35_program_surface_config(
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struct hubp *hubp,
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enum surface_pixel_format format,
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union dc_tiling_info *tiling_info,
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struct plane_size *plane_size,
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enum dc_rotation_angle rotation,
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struct dc_plane_dcc_param *dcc,
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bool horizontal_mirror,
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unsigned int compat_level);
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#endif /* __DC_HUBP_DCN35_H__ */
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