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ARM: at91: Remove reset code from the machine code

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Now that the transition is over and that we probe our reset driver in every
case, we can remove the legacy code from the machine directory.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Maxime Ripard 2014-07-03 12:00:52 +02:00 committed by Nicolas Ferre
parent e76265c627
commit 99d63fa1c8
10 changed files with 0 additions and 102 deletions
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8
arch/arm/mach-at91/Kconfig
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@ -33,14 +33,6 @@ config OLD_IRQ_AT91
select MULTI_IRQ_HANDLER select MULTI_IRQ_HANDLER
select SPARSE_IRQ select SPARSE_IRQ
config AT91_SAM9_ALT_RESET
bool
default !ARCH_AT91X40
config AT91_SAM9G45_RESET
bool
default !ARCH_AT91X40
config AT91_SAM9_TIME config AT91_SAM9_TIME
bool bool

2
arch/arm/mach-at91/Makefile
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@ -9,8 +9,6 @@ obj- :=
obj-$(CONFIG_OLD_IRQ_AT91) += irq.o obj-$(CONFIG_OLD_IRQ_AT91) += irq.o
obj-$(CONFIG_OLD_CLK_AT91) += clock.o obj-$(CONFIG_OLD_CLK_AT91) += clock.o
obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o
obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o

1
arch/arm/mach-at91/at91sam9260.c
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@ -355,7 +355,6 @@ static void __init at91sam9260_ioremap_registers(void)
static void __init at91sam9260_initialize(void) static void __init at91sam9260_initialize(void)
{ {
arm_pm_idle = at91sam9_idle; arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart;
at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT); at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);

1
arch/arm/mach-at91/at91sam9261.c
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@ -314,7 +314,6 @@ static void __init at91sam9261_ioremap_registers(void)
static void __init at91sam9261_initialize(void) static void __init at91sam9261_initialize(void)
{ {
arm_pm_idle = at91sam9_idle; arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart;
at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT); at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);

1
arch/arm/mach-at91/at91sam9263.c
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@ -336,7 +336,6 @@ static void __init at91sam9263_ioremap_registers(void)
static void __init at91sam9263_initialize(void) static void __init at91sam9263_initialize(void)
{ {
arm_pm_idle = at91sam9_idle; arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart;
at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0); at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1); at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);

40
arch/arm/mach-at91/at91sam9_alt_reset.S
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@ -1,40 +0,0 @@
/*
* reset AT91SAM9G20 as per errata
*
* (C) BitBox Ltd 2010
*
* unless the SDRAM is cleanly shutdown before we hit the
* reset register it can be left driving the data bus and
* killing the chance of a subsequent boot from NAND
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/linkage.h>
#include <mach/hardware.h>
#include <mach/at91_ramc.h>
#include "at91_rstc.h"
.arm
.globl at91sam9_alt_restart
at91sam9_alt_restart: ldr r0, =at91_ramc_base @ preload constants
ldr r0, [r0]
ldr r4, =at91_rstc_base
ldr r1, [r4]
mov r2, #1
mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
.balign 32 @ align to cache line
str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access
str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM
str r4, [r1, #AT91_RSTC_CR] @ reset processor
b .

1
arch/arm/mach-at91/at91sam9g45.c
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@ -385,7 +385,6 @@ static void __init at91sam9g45_ioremap_registers(void)
static void __init at91sam9g45_initialize(void) static void __init at91sam9g45_initialize(void)
{ {
arm_pm_idle = at91sam9_idle; arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9g45_restart;
at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC); at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT); at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);

45
arch/arm/mach-at91/at91sam9g45_reset.S
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@ -1,45 +0,0 @@
/*
* reset AT91SAM9G45 as per errata
*
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
*
* unless the SDRAM is cleanly shutdown before we hit the
* reset register it can be left driving the data bus and
* killing the chance of a subsequent boot from NAND
*
* GPLv2 Only
*/
#include <linux/linkage.h>
#include <mach/hardware.h>
#include <mach/at91_ramc.h>
#include "at91_rstc.h"
.arm
/*
* at91_ramc_base is an array void*
* init at NULL if only one DDR controler is present in or DT
*/
.globl at91sam9g45_restart
at91sam9g45_restart:
ldr r5, =at91_ramc_base @ preload constants
ldr r0, [r5]
ldr r5, [r5, #4] @ ddr1
cmp r5, #0
ldr r4, =at91_rstc_base
ldr r1, [r4]
mov r2, #1
mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
.balign 32 @ align to cache line
strne r2, [r5, #AT91_DDRSDRC_RTR] @ disable DDR1 access
strne r3, [r5, #AT91_DDRSDRC_LPR] @ power down DDR1
str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
str r4, [r1, #AT91_RSTC_CR] @ reset processor
b .

1
arch/arm/mach-at91/at91sam9rl.c
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@ -324,7 +324,6 @@ static void __init at91sam9rl_ioremap_registers(void)
static void __init at91sam9rl_initialize(void) static void __init at91sam9rl_initialize(void)
{ {
arm_pm_idle = at91sam9_idle; arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart;
at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC); at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT); at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);

2
arch/arm/mach-at91/generic.h
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@ -66,8 +66,6 @@ extern void at91sam9_idle(void);
/* reset */ /* reset */
extern void at91_ioremap_rstc(u32 base_addr); extern void at91_ioremap_rstc(u32 base_addr);
extern void at91sam9_alt_restart(enum reboot_mode, const char *);
extern void at91sam9g45_restart(enum reboot_mode, const char *);
/* shutdown */ /* shutdown */
extern void at91_ioremap_shdwc(u32 base_addr); extern void at91_ioremap_shdwc(u32 base_addr);