drm/amd/display: Decouple amdgpu_dm_trace from service
Our DC currently uses some of the tracepoint function inside a DC header, which means that many other files implicitly include part of the trace function. This situation limits how we can expand this feature for other parts of the driver by generating multiple compilation errors when we try to reuse some of the existing structures. This commit decouples part of the amdgpu_dm_trace from DC core to simplify the trace enlargement in future changes. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -34,6 +34,7 @@
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#include "dc/inc/hw/dmcu.h"
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#include "dc/inc/hw/abm.h"
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#include "dc/dc_dmub_srv.h"
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#include "amdgpu_dm_trace.h"
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#include "vid.h"
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#include "amdgpu.h"
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@ -9243,3 +9244,41 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
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}
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mutex_unlock(&adev->dm.dc_lock);
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}
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void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
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uint32_t value, const char *func_name)
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{
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#ifdef DM_CHECK_ADDR_0
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if (address == 0) {
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DC_ERR("invalid register write. address = 0");
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return;
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}
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#endif
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cgs_write_register(ctx->cgs_device, address, value);
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trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
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}
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uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
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const char *func_name)
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{
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uint32_t value;
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#ifdef DM_CHECK_ADDR_0
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if (address == 0) {
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DC_ERR("invalid register read; address = 0\n");
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return 0;
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}
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#endif
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if (ctx->dmub_srv &&
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ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
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!ctx->dmub_srv->reg_helper_offload.should_burst_write) {
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ASSERT(false);
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return 0;
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}
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value = cgs_read_register(ctx->cgs_device, address);
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trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
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return value;
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}
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@ -33,18 +33,23 @@
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#include "amdgpu_dm.h"
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#include "amdgpu_dm_irq.h"
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#include "amdgpu_pm.h"
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#include "amdgpu_dm_trace.h"
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unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
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unsigned long long current_time_stamp,
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unsigned long long last_time_stamp)
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unsigned long long
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dm_get_elapse_time_in_ns(struct dc_context *ctx,
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unsigned long long current_time_stamp,
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unsigned long long last_time_stamp)
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{
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return current_time_stamp - last_time_stamp;
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}
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void dm_perf_trace_timestamp(const char *func_name, unsigned int line)
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void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc_context *ctx)
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{
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trace_amdgpu_dc_performance(ctx->perf_trace->read_count,
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ctx->perf_trace->write_count,
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&ctx->perf_trace->last_entry_read,
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&ctx->perf_trace->last_entry_write,
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func_name, line);
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}
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/**** power component interfaces ****/
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@ -26,7 +26,7 @@
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#undef TRACE_SYSTEM
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#define TRACE_SYSTEM amdgpu_dm
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#if !defined(_AMDGPU_DM_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
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#if !defined(_AMDGPU_DM_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
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#define _AMDGPU_DM_TRACE_H_
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#include <linux/tracepoint.h>
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@ -296,32 +296,6 @@ uint32_t generic_reg_set_ex(const struct dc_context *ctx,
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return reg_val;
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}
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uint32_t dm_read_reg_func(
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const struct dc_context *ctx,
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uint32_t address,
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const char *func_name)
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{
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uint32_t value;
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#ifdef DM_CHECK_ADDR_0
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if (address == 0) {
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DC_ERR("invalid register read; address = 0\n");
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return 0;
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}
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#endif
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if (ctx->dmub_srv &&
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ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
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!ctx->dmub_srv->reg_helper_offload.should_burst_write) {
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ASSERT(false);
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return 0;
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}
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value = cgs_read_register(ctx->cgs_device, address);
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trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
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return value;
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}
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uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
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uint8_t shift, uint32_t mask, uint32_t *field_value)
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{
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@ -31,8 +31,6 @@
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#define __DM_SERVICES_H__
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#include "amdgpu_dm_trace.h"
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/* TODO: remove when DC is complete. */
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#include "dm_services_types.h"
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#include "logger_interface.h"
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@ -49,43 +47,26 @@ irq_handler_idx dm_register_interrupt(
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interrupt_handler ih,
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void *handler_args);
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/*
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*
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* GPU registers access
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*
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*/
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uint32_t dm_read_reg_func(
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const struct dc_context *ctx,
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uint32_t address,
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const char *func_name);
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uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
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const char *func_name);
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/* enable for debugging new code, this adds 50k to the driver size. */
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/* #define DM_CHECK_ADDR_0 */
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void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
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uint32_t value, const char *func_name);
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#define dm_read_reg(ctx, address) \
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dm_read_reg_func(ctx, address, __func__)
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dm_read_reg_func(ctx, address, __func__)
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#define dm_write_reg(ctx, address, value) \
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dm_write_reg_func(ctx, address, value, __func__)
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static inline void dm_write_reg_func(
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const struct dc_context *ctx,
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uint32_t address,
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uint32_t value,
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const char *func_name)
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{
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#ifdef DM_CHECK_ADDR_0
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if (address == 0) {
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DC_ERR("invalid register write. address = 0");
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return;
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}
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#endif
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cgs_write_register(ctx->cgs_device, address, value);
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trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
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}
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static inline uint32_t dm_read_index_reg(
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const struct dc_context *ctx,
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enum cgs_ind_reg addr_space,
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@ -287,13 +268,10 @@ unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
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/*
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* performance tracing
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*/
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#define PERF_TRACE() trace_amdgpu_dc_performance(CTX->perf_trace->read_count,\
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CTX->perf_trace->write_count, &CTX->perf_trace->last_entry_read,\
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&CTX->perf_trace->last_entry_write, __func__, __LINE__)
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#define PERF_TRACE_CTX(__CTX) trace_amdgpu_dc_performance(__CTX->perf_trace->read_count,\
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__CTX->perf_trace->write_count, &__CTX->perf_trace->last_entry_read,\
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&__CTX->perf_trace->last_entry_write, __func__, __LINE__)
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void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc_context *ctx);
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#define PERF_TRACE() dm_perf_trace_timestamp(__func__, __LINE__, CTX)
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#define PERF_TRACE_CTX(__CTX) dm_perf_trace_timestamp(__func__, __LINE__, __CTX)
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/*
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* Debug and verification hooks
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