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Merge tag 'ib-mfd-tps6594-core-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into char-misc-next

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Immutable branch containing TPS6594 core (MFD) support due for the v6.5 merge window

We want this due to patches requiring this mfd support.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

* tag 'ib-mfd-tps6594-core-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd:
  mfd: tps6594: Add driver for TI TPS6594 PMIC
This commit is contained in:
Greg Kroah-Hartman
2023-06-15 13:39:13 +02:00
parent e04b1bff33 325bec7157
commit 9fb908040a
6 changed files with 1890 additions and 0 deletions
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32
drivers/mfd/Kconfig
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@@ -1679,6 +1679,38 @@ config MFD_TPS65912_SPI
If you say yes here you get support for the TPS65912 series of
PM chips with SPI interface.
config MFD_TPS6594
tristate
select MFD_CORE
select REGMAP
select REGMAP_IRQ
config MFD_TPS6594_I2C
tristate "TI TPS6594 Power Management chip with I2C"
select MFD_TPS6594
select REGMAP_I2C
select CRC8
depends on I2C
help
If you say yes here you get support for the TPS6594 series of
PM chips with I2C interface.
This driver can also be built as a module. If so, the module
will be called tps6594-i2c.
config MFD_TPS6594_SPI
tristate "TI TPS6594 Power Management chip with SPI"
select MFD_TPS6594
select REGMAP_SPI
select CRC8
depends on SPI_MASTER
help
If you say yes here you get support for the TPS6594 series of
PM chips with SPI interface.
This driver can also be built as a module. If so, the module
will be called tps6594-spi.
config TWL4030_CORE
bool "TI TWL4030/TWL5030/TWL6030/TPS659x0 Support"
depends on I2C=y

3
drivers/mfd/Makefile
View File

@@ -96,6 +96,9 @@ obj-$(CONFIG_MFD_TPS65910) += tps65910.o
obj-$(CONFIG_MFD_TPS65912) += tps65912-core.o
obj-$(CONFIG_MFD_TPS65912_I2C) += tps65912-i2c.o
obj-$(CONFIG_MFD_TPS65912_SPI) += tps65912-spi.o
obj-$(CONFIG_MFD_TPS6594) += tps6594-core.o
obj-$(CONFIG_MFD_TPS6594_I2C) += tps6594-i2c.o
obj-$(CONFIG_MFD_TPS6594_SPI) += tps6594-spi.o
obj-$(CONFIG_MENELAUS) += menelaus.o
obj-$(CONFIG_TWL4030_CORE) += twl-core.o twl4030-irq.o twl6030-irq.o

462
drivers/mfd/tps6594-core.c Normal file
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@@ -0,0 +1,462 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Core functions for TI TPS6594/TPS6593/LP8764 PMICs
*
* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
*/
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tps6594.h>
#define TPS6594_CRC_SYNC_TIMEOUT_MS 150
/* Completion to synchronize CRC feature enabling on all PMICs */
static DECLARE_COMPLETION(tps6594_crc_comp);
static const struct resource tps6594_regulator_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_OV, TPS6594_IRQ_NAME_BUCK1_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_UV, TPS6594_IRQ_NAME_BUCK1_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_SC, TPS6594_IRQ_NAME_BUCK1_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_ILIM, TPS6594_IRQ_NAME_BUCK1_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_OV, TPS6594_IRQ_NAME_BUCK2_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_UV, TPS6594_IRQ_NAME_BUCK2_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_SC, TPS6594_IRQ_NAME_BUCK2_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_ILIM, TPS6594_IRQ_NAME_BUCK2_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_OV, TPS6594_IRQ_NAME_BUCK3_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_UV, TPS6594_IRQ_NAME_BUCK3_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_SC, TPS6594_IRQ_NAME_BUCK3_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_ILIM, TPS6594_IRQ_NAME_BUCK3_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_OV, TPS6594_IRQ_NAME_BUCK4_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_UV, TPS6594_IRQ_NAME_BUCK4_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_SC, TPS6594_IRQ_NAME_BUCK4_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_ILIM, TPS6594_IRQ_NAME_BUCK4_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_OV, TPS6594_IRQ_NAME_BUCK5_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_UV, TPS6594_IRQ_NAME_BUCK5_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_SC, TPS6594_IRQ_NAME_BUCK5_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_ILIM, TPS6594_IRQ_NAME_BUCK5_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_OV, TPS6594_IRQ_NAME_LDO1_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_UV, TPS6594_IRQ_NAME_LDO1_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_SC, TPS6594_IRQ_NAME_LDO1_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_ILIM, TPS6594_IRQ_NAME_LDO1_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_OV, TPS6594_IRQ_NAME_LDO2_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_UV, TPS6594_IRQ_NAME_LDO2_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_SC, TPS6594_IRQ_NAME_LDO2_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_ILIM, TPS6594_IRQ_NAME_LDO2_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_OV, TPS6594_IRQ_NAME_LDO3_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_UV, TPS6594_IRQ_NAME_LDO3_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_SC, TPS6594_IRQ_NAME_LDO3_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_ILIM, TPS6594_IRQ_NAME_LDO3_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_OV, TPS6594_IRQ_NAME_LDO4_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_UV, TPS6594_IRQ_NAME_LDO4_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_SC, TPS6594_IRQ_NAME_LDO4_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_ILIM, TPS6594_IRQ_NAME_LDO4_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_OV, TPS6594_IRQ_NAME_VCCA_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_UV, TPS6594_IRQ_NAME_VCCA_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_OV, TPS6594_IRQ_NAME_VMON1_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_UV, TPS6594_IRQ_NAME_VMON1_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_RV, TPS6594_IRQ_NAME_VMON1_RV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_OV, TPS6594_IRQ_NAME_VMON2_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_UV, TPS6594_IRQ_NAME_VMON2_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_RV, TPS6594_IRQ_NAME_VMON2_RV),
};
static const struct resource tps6594_pinctrl_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO9, TPS6594_IRQ_NAME_GPIO9),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO10, TPS6594_IRQ_NAME_GPIO10),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO11, TPS6594_IRQ_NAME_GPIO11),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO1, TPS6594_IRQ_NAME_GPIO1),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO2, TPS6594_IRQ_NAME_GPIO2),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO3, TPS6594_IRQ_NAME_GPIO3),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO4, TPS6594_IRQ_NAME_GPIO4),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO5, TPS6594_IRQ_NAME_GPIO5),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO6, TPS6594_IRQ_NAME_GPIO6),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO7, TPS6594_IRQ_NAME_GPIO7),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO8, TPS6594_IRQ_NAME_GPIO8),
};
static const struct resource tps6594_pfsm_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NPWRON_START, TPS6594_IRQ_NAME_NPWRON_START),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ENABLE, TPS6594_IRQ_NAME_ENABLE),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_FSD, TPS6594_IRQ_NAME_FSD),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SOFT_REBOOT, TPS6594_IRQ_NAME_SOFT_REBOOT),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BIST_PASS, TPS6594_IRQ_NAME_BIST_PASS),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_EXT_CLK, TPS6594_IRQ_NAME_EXT_CLK),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TWARN, TPS6594_IRQ_NAME_TWARN),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TSD_ORD, TPS6594_IRQ_NAME_TSD_ORD),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BIST_FAIL, TPS6594_IRQ_NAME_BIST_FAIL),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_REG_CRC_ERR, TPS6594_IRQ_NAME_REG_CRC_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_RECOV_CNT, TPS6594_IRQ_NAME_RECOV_CNT),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SPMI_ERR, TPS6594_IRQ_NAME_SPMI_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NPWRON_LONG, TPS6594_IRQ_NAME_NPWRON_LONG),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NINT_READBACK, TPS6594_IRQ_NAME_NINT_READBACK),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NRSTOUT_READBACK, TPS6594_IRQ_NAME_NRSTOUT_READBACK),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TSD_IMM, TPS6594_IRQ_NAME_TSD_IMM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_OVP, TPS6594_IRQ_NAME_VCCA_OVP),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_PFSM_ERR, TPS6594_IRQ_NAME_PFSM_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_IMM_SHUTDOWN, TPS6594_IRQ_NAME_IMM_SHUTDOWN),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ORD_SHUTDOWN, TPS6594_IRQ_NAME_ORD_SHUTDOWN),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_MCU_PWR_ERR, TPS6594_IRQ_NAME_MCU_PWR_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SOC_PWR_ERR, TPS6594_IRQ_NAME_SOC_PWR_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_FRM_ERR, TPS6594_IRQ_NAME_COMM_FRM_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_CRC_ERR, TPS6594_IRQ_NAME_COMM_CRC_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_ADR_ERR, TPS6594_IRQ_NAME_COMM_ADR_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_EN_DRV_READBACK, TPS6594_IRQ_NAME_EN_DRV_READBACK),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NRSTOUT_SOC_READBACK,
TPS6594_IRQ_NAME_NRSTOUT_SOC_READBACK),
};
static const struct resource tps6594_esm_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_PIN, TPS6594_IRQ_NAME_ESM_SOC_PIN),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_FAIL, TPS6594_IRQ_NAME_ESM_SOC_FAIL),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_RST, TPS6594_IRQ_NAME_ESM_SOC_RST),
};
static const struct resource tps6594_rtc_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TIMER, TPS6594_IRQ_NAME_TIMER),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ALARM, TPS6594_IRQ_NAME_ALARM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_POWER_UP, TPS6594_IRQ_NAME_POWERUP),
};
static const struct mfd_cell tps6594_common_cells[] = {
MFD_CELL_RES("tps6594-regulator", tps6594_regulator_resources),
MFD_CELL_RES("tps6594-pinctrl", tps6594_pinctrl_resources),
MFD_CELL_RES("tps6594-pfsm", tps6594_pfsm_resources),
MFD_CELL_RES("tps6594-esm", tps6594_esm_resources),
};
static const struct mfd_cell tps6594_rtc_cells[] = {
MFD_CELL_RES("tps6594-rtc", tps6594_rtc_resources),
};
static const struct regmap_irq tps6594_irqs[] = {
/* INT_BUCK1_2 register */
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_OV, 0, TPS6594_BIT_BUCKX_OV_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_UV, 0, TPS6594_BIT_BUCKX_UV_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_SC, 0, TPS6594_BIT_BUCKX_SC_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_ILIM, 0, TPS6594_BIT_BUCKX_ILIM_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_OV, 0, TPS6594_BIT_BUCKX_OV_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_UV, 0, TPS6594_BIT_BUCKX_UV_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_SC, 0, TPS6594_BIT_BUCKX_SC_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_ILIM, 0, TPS6594_BIT_BUCKX_ILIM_INT(1)),
/* INT_BUCK3_4 register */
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_OV, 1, TPS6594_BIT_BUCKX_OV_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_UV, 1, TPS6594_BIT_BUCKX_UV_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_SC, 1, TPS6594_BIT_BUCKX_SC_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_ILIM, 1, TPS6594_BIT_BUCKX_ILIM_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_OV, 1, TPS6594_BIT_BUCKX_OV_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_UV, 1, TPS6594_BIT_BUCKX_UV_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_SC, 1, TPS6594_BIT_BUCKX_SC_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_ILIM, 1, TPS6594_BIT_BUCKX_ILIM_INT(3)),
/* INT_BUCK5 register */
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_OV, 2, TPS6594_BIT_BUCKX_OV_INT(4)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_UV, 2, TPS6594_BIT_BUCKX_UV_INT(4)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_SC, 2, TPS6594_BIT_BUCKX_SC_INT(4)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_ILIM, 2, TPS6594_BIT_BUCKX_ILIM_INT(4)),
/* INT_LDO1_2 register */
REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_OV, 3, TPS6594_BIT_LDOX_OV_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_UV, 3, TPS6594_BIT_LDOX_UV_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_SC, 3, TPS6594_BIT_LDOX_SC_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_ILIM, 3, TPS6594_BIT_LDOX_ILIM_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_OV, 3, TPS6594_BIT_LDOX_OV_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_UV, 3, TPS6594_BIT_LDOX_UV_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_SC, 3, TPS6594_BIT_LDOX_SC_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_ILIM, 3, TPS6594_BIT_LDOX_ILIM_INT(1)),
/* INT_LDO3_4 register */
REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_OV, 4, TPS6594_BIT_LDOX_OV_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_UV, 4, TPS6594_BIT_LDOX_UV_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_SC, 4, TPS6594_BIT_LDOX_SC_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_ILIM, 4, TPS6594_BIT_LDOX_ILIM_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_OV, 4, TPS6594_BIT_LDOX_OV_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_UV, 4, TPS6594_BIT_LDOX_UV_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_SC, 4, TPS6594_BIT_LDOX_SC_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_ILIM, 4, TPS6594_BIT_LDOX_ILIM_INT(3)),
/* INT_VMON register */
REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_OV, 5, TPS6594_BIT_VCCA_OV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_UV, 5, TPS6594_BIT_VCCA_UV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_OV, 5, TPS6594_BIT_VMON1_OV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_UV, 5, TPS6594_BIT_VMON1_UV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_RV, 5, TPS6594_BIT_VMON1_RV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_OV, 5, TPS6594_BIT_VMON2_OV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_UV, 5, TPS6594_BIT_VMON2_UV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_RV, 5, TPS6594_BIT_VMON2_RV_INT),
/* INT_GPIO register */
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO9, 6, TPS6594_BIT_GPIO9_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO10, 6, TPS6594_BIT_GPIO10_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO11, 6, TPS6594_BIT_GPIO11_INT),
/* INT_GPIO1_8 register */
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO1, 7, TPS6594_BIT_GPIOX_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO2, 7, TPS6594_BIT_GPIOX_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO3, 7, TPS6594_BIT_GPIOX_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO4, 7, TPS6594_BIT_GPIOX_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO5, 7, TPS6594_BIT_GPIOX_INT(4)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO6, 7, TPS6594_BIT_GPIOX_INT(5)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO7, 7, TPS6594_BIT_GPIOX_INT(6)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO8, 7, TPS6594_BIT_GPIOX_INT(7)),
/* INT_STARTUP register */
REGMAP_IRQ_REG(TPS6594_IRQ_NPWRON_START, 8, TPS6594_BIT_NPWRON_START_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_ENABLE, 8, TPS6594_BIT_ENABLE_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_FSD, 8, TPS6594_BIT_FSD_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_SOFT_REBOOT, 8, TPS6594_BIT_SOFT_REBOOT_INT),
/* INT_MISC register */
REGMAP_IRQ_REG(TPS6594_IRQ_BIST_PASS, 9, TPS6594_BIT_BIST_PASS_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_EXT_CLK, 9, TPS6594_BIT_EXT_CLK_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_TWARN, 9, TPS6594_BIT_TWARN_INT),
/* INT_MODERATE_ERR register */
REGMAP_IRQ_REG(TPS6594_IRQ_TSD_ORD, 10, TPS6594_BIT_TSD_ORD_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_BIST_FAIL, 10, TPS6594_BIT_BIST_FAIL_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_REG_CRC_ERR, 10, TPS6594_BIT_REG_CRC_ERR_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_RECOV_CNT, 10, TPS6594_BIT_RECOV_CNT_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_SPMI_ERR, 10, TPS6594_BIT_SPMI_ERR_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_NPWRON_LONG, 10, TPS6594_BIT_NPWRON_LONG_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_NINT_READBACK, 10, TPS6594_BIT_NINT_READBACK_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_NRSTOUT_READBACK, 10, TPS6594_BIT_NRSTOUT_READBACK_INT),
/* INT_SEVERE_ERR register */
REGMAP_IRQ_REG(TPS6594_IRQ_TSD_IMM, 11, TPS6594_BIT_TSD_IMM_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_OVP, 11, TPS6594_BIT_VCCA_OVP_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_PFSM_ERR, 11, TPS6594_BIT_PFSM_ERR_INT),
/* INT_FSM_ERR register */
REGMAP_IRQ_REG(TPS6594_IRQ_IMM_SHUTDOWN, 12, TPS6594_BIT_IMM_SHUTDOWN_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_ORD_SHUTDOWN, 12, TPS6594_BIT_ORD_SHUTDOWN_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_MCU_PWR_ERR, 12, TPS6594_BIT_MCU_PWR_ERR_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_SOC_PWR_ERR, 12, TPS6594_BIT_SOC_PWR_ERR_INT),
/* INT_COMM_ERR register */
REGMAP_IRQ_REG(TPS6594_IRQ_COMM_FRM_ERR, 13, TPS6594_BIT_COMM_FRM_ERR_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_COMM_CRC_ERR, 13, TPS6594_BIT_COMM_CRC_ERR_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_COMM_ADR_ERR, 13, TPS6594_BIT_COMM_ADR_ERR_INT),
/* INT_READBACK_ERR register */
REGMAP_IRQ_REG(TPS6594_IRQ_EN_DRV_READBACK, 14, TPS6594_BIT_EN_DRV_READBACK_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_NRSTOUT_SOC_READBACK, 14, TPS6594_BIT_NRSTOUT_SOC_READBACK_INT),
/* INT_ESM register */
REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_PIN, 15, TPS6594_BIT_ESM_SOC_PIN_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_FAIL, 15, TPS6594_BIT_ESM_SOC_FAIL_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_RST, 15, TPS6594_BIT_ESM_SOC_RST_INT),
/* RTC_STATUS register */
REGMAP_IRQ_REG(TPS6594_IRQ_TIMER, 16, TPS6594_BIT_TIMER),
REGMAP_IRQ_REG(TPS6594_IRQ_ALARM, 16, TPS6594_BIT_ALARM),
REGMAP_IRQ_REG(TPS6594_IRQ_POWER_UP, 16, TPS6594_BIT_POWER_UP),
};
static const unsigned int tps6594_irq_reg[] = {
TPS6594_REG_INT_BUCK1_2,
TPS6594_REG_INT_BUCK3_4,
TPS6594_REG_INT_BUCK5,
TPS6594_REG_INT_LDO1_2,
TPS6594_REG_INT_LDO3_4,
TPS6594_REG_INT_VMON,
TPS6594_REG_INT_GPIO,
TPS6594_REG_INT_GPIO1_8,
TPS6594_REG_INT_STARTUP,
TPS6594_REG_INT_MISC,
TPS6594_REG_INT_MODERATE_ERR,
TPS6594_REG_INT_SEVERE_ERR,
TPS6594_REG_INT_FSM_ERR,
TPS6594_REG_INT_COMM_ERR,
TPS6594_REG_INT_READBACK_ERR,
TPS6594_REG_INT_ESM,
TPS6594_REG_RTC_STATUS,
};
static inline unsigned int tps6594_get_irq_reg(struct regmap_irq_chip_data *data,
unsigned int base, int index)
{
return tps6594_irq_reg[index];
};
static int tps6594_handle_post_irq(void *irq_drv_data)
{
struct tps6594 *tps = irq_drv_data;
int ret = 0;
/*
* When CRC is enabled, writing to a read-only bit triggers an error,
* and COMM_ADR_ERR_INT bit is set. Besides, bits indicating interrupts
* (that must be cleared) and read-only bits are sometimes grouped in
* the same register.
* Since regmap clears interrupts by doing a write per register, clearing
* an interrupt bit in a register containing also a read-only bit makes
* COMM_ADR_ERR_INT bit set. Clear immediately this bit to avoid raising
* a new interrupt.
*/
if (tps->use_crc)
ret = regmap_write_bits(tps->regmap, TPS6594_REG_INT_COMM_ERR,
TPS6594_BIT_COMM_ADR_ERR_INT,
TPS6594_BIT_COMM_ADR_ERR_INT);
return ret;
};
static struct regmap_irq_chip tps6594_irq_chip = {
.ack_base = TPS6594_REG_INT_BUCK1_2,
.ack_invert = 1,
.clear_ack = 1,
.init_ack_masked = 1,
.num_regs = ARRAY_SIZE(tps6594_irq_reg),
.irqs = tps6594_irqs,
.num_irqs = ARRAY_SIZE(tps6594_irqs),
.get_irq_reg = tps6594_get_irq_reg,
.handle_post_irq = tps6594_handle_post_irq,
};
bool tps6594_is_volatile_reg(struct device *dev, unsigned int reg)
{
return (reg >= TPS6594_REG_INT_TOP && reg <= TPS6594_REG_STAT_READBACK_ERR) ||
reg == TPS6594_REG_RTC_STATUS;
}
EXPORT_SYMBOL_GPL(tps6594_is_volatile_reg);
static int tps6594_check_crc_mode(struct tps6594 *tps, bool primary_pmic)
{
int ret;
/*
* Check if CRC is enabled.
* Once CRC is enabled, it can't be disabled until next power cycle.
*/
tps->use_crc = true;
ret = regmap_test_bits(tps->regmap, TPS6594_REG_SERIAL_IF_CONFIG,
TPS6594_BIT_I2C1_SPI_CRC_EN);
if (ret == 0) {
ret = -EIO;
} else if (ret > 0) {
dev_info(tps->dev, "CRC feature enabled on %s PMIC",
primary_pmic ? "primary" : "secondary");
ret = 0;
}
return ret;
}
static int tps6594_set_crc_feature(struct tps6594 *tps)
{
int ret;
ret = tps6594_check_crc_mode(tps, true);
if (ret) {
/*
* If CRC is not already enabled, force PFSM I2C_2 trigger to enable it
* on primary PMIC.
*/
tps->use_crc = false;
ret = regmap_write_bits(tps->regmap, TPS6594_REG_FSM_I2C_TRIGGERS,
TPS6594_BIT_TRIGGER_I2C(2), TPS6594_BIT_TRIGGER_I2C(2));
if (ret)
return ret;
/*
* Wait for PFSM to process trigger.
* The datasheet indicates 2 ms, and clock specification is +/-5%.
* 4 ms should provide sufficient margin.
*/
usleep_range(4000, 5000);
ret = tps6594_check_crc_mode(tps, true);
}
return ret;
}
static int tps6594_enable_crc(struct tps6594 *tps)
{
struct device *dev = tps->dev;
unsigned int is_primary;
unsigned long timeout = msecs_to_jiffies(TPS6594_CRC_SYNC_TIMEOUT_MS);
int ret;
/*
* CRC mode can be used with I2C or SPI protocols.
* If this mode is specified for primary PMIC, it will also be applied to secondary PMICs
* through SPMI serial interface.
* In this multi-PMIC synchronization scheme, the primary PMIC is the controller device
* on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus.
*/
is_primary = of_property_read_bool(dev->of_node, "ti,primary-pmic");
if (is_primary) {
/* Enable CRC feature on primary PMIC */
ret = tps6594_set_crc_feature(tps);
if (ret)
return ret;
/* Notify secondary PMICs that CRC feature is enabled */
complete_all(&tps6594_crc_comp);
} else {
/* Wait for CRC feature enabling event from primary PMIC */
ret = wait_for_completion_interruptible_timeout(&tps6594_crc_comp, timeout);
if (ret == 0)
ret = -ETIMEDOUT;
else if (ret > 0)
ret = tps6594_check_crc_mode(tps, false);
}
return ret;
}
int tps6594_device_init(struct tps6594 *tps, bool enable_crc)
{
struct device *dev = tps->dev;
int ret;
if (enable_crc) {
ret = tps6594_enable_crc(tps);
if (ret)
return dev_err_probe(dev, ret, "Failed to enable CRC\n");
}
/* Keep PMIC in ACTIVE state */
ret = regmap_set_bits(tps->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS,
TPS6594_BIT_NSLEEP1B | TPS6594_BIT_NSLEEP2B);
if (ret)
return dev_err_probe(dev, ret, "Failed to set PMIC state\n");
tps6594_irq_chip.irq_drv_data = tps;
tps6594_irq_chip.name = devm_kasprintf(dev, GFP_KERNEL, "%s-%ld-0x%02x",
dev->driver->name, tps->chip_id, tps->reg);
ret = devm_regmap_add_irq_chip(dev, tps->regmap, tps->irq, IRQF_SHARED | IRQF_ONESHOT,
0, &tps6594_irq_chip, &tps->irq_data);
if (ret)
return dev_err_probe(dev, ret, "Failed to add regmap IRQ\n");
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, tps6594_common_cells,
ARRAY_SIZE(tps6594_common_cells), NULL, 0,
regmap_irq_get_domain(tps->irq_data));
if (ret)
return dev_err_probe(dev, ret, "Failed to add common child devices\n");
/* No RTC for LP8764 */
if (tps->chip_id != LP8764) {
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, tps6594_rtc_cells,
ARRAY_SIZE(tps6594_rtc_cells), NULL, 0,
regmap_irq_get_domain(tps->irq_data));
if (ret)
return dev_err_probe(dev, ret, "Failed to add RTC child device\n");
}
return 0;
}
EXPORT_SYMBOL_GPL(tps6594_device_init);
MODULE_AUTHOR("Julien Panis <jpanis@baylibre.com>");
MODULE_DESCRIPTION("TPS6594 Driver");
MODULE_LICENSE("GPL");

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drivers/mfd/tps6594-i2c.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* I2C access driver for TI TPS6594/TPS6593/LP8764 PMICs
*
* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
*/
#include <linux/crc8.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/mfd/tps6594.h>
static bool enable_crc;
module_param(enable_crc, bool, 0444);
MODULE_PARM_DESC(enable_crc, "Enable CRC feature for I2C interface");
DECLARE_CRC8_TABLE(tps6594_i2c_crc_table);
static int tps6594_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
int ret = i2c_transfer(adap, msgs, num);
if (ret == num)
return 0;
else if (ret < 0)
return ret;
else
return -EIO;
}
static int tps6594_i2c_reg_read_with_crc(struct i2c_client *client, u8 page, u8 reg, u8 *val)
{
struct i2c_msg msgs[2];
u8 buf_rx[] = { 0, 0 };
/* I2C address = I2C base address + Page index */
const u8 addr = client->addr + page;
/*
* CRC is calculated from every bit included in the protocol
* except the ACK bits from the target. Byte stream is:
* - B0: (I2C_addr_7bits << 1) | WR_bit, with WR_bit = 0
* - B1: reg
* - B2: (I2C_addr_7bits << 1) | RD_bit, with RD_bit = 1
* - B3: val
* - B4: CRC from B0-B1-B2-B3
*/
u8 crc_data[] = { addr << 1, reg, addr << 1 | 1, 0 };
int ret;
/* Write register */
msgs[0].addr = addr;
msgs[0].flags = 0;
msgs[0].len = 1;
msgs[0].buf = &reg;
/* Read data and CRC */
msgs[1].addr = msgs[0].addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = 2;
msgs[1].buf = buf_rx;
ret = tps6594_i2c_transfer(client->adapter, msgs, 2);
if (ret < 0)
return ret;
crc_data[sizeof(crc_data) - 1] = *val = buf_rx[0];
if (buf_rx[1] != crc8(tps6594_i2c_crc_table, crc_data, sizeof(crc_data), CRC8_INIT_VALUE))
return -EIO;
return ret;
}
static int tps6594_i2c_reg_write_with_crc(struct i2c_client *client, u8 page, u8 reg, u8 val)
{
struct i2c_msg msg;
u8 buf[] = { reg, val, 0 };
/* I2C address = I2C base address + Page index */
const u8 addr = client->addr + page;
/*
* CRC is calculated from every bit included in the protocol
* except the ACK bits from the target. Byte stream is:
* - B0: (I2C_addr_7bits << 1) | WR_bit, with WR_bit = 0
* - B1: reg
* - B2: val
* - B3: CRC from B0-B1-B2
*/
const u8 crc_data[] = { addr << 1, reg, val };
/* Write register, data and CRC */
msg.addr = addr;
msg.flags = client->flags & I2C_M_TEN;
msg.len = sizeof(buf);
msg.buf = buf;
buf[msg.len - 1] = crc8(tps6594_i2c_crc_table, crc_data, sizeof(crc_data), CRC8_INIT_VALUE);
return tps6594_i2c_transfer(client->adapter, &msg, 1);
}
static int tps6594_i2c_read(void *context, const void *reg_buf, size_t reg_size,
void *val_buf, size_t val_size)
{
struct i2c_client *client = context;
struct tps6594 *tps = i2c_get_clientdata(client);
struct i2c_msg msgs[2];
const u8 *reg_bytes = reg_buf;
u8 *val_bytes = val_buf;
const u8 page = reg_bytes[1];
u8 reg = reg_bytes[0];
int ret = 0;
int i;
if (tps->use_crc) {
/*
* Auto-increment feature does not support CRC protocol.
* Converts the bulk read operation into a series of single read operations.
*/
for (i = 0 ; ret == 0 && i < val_size ; i++)
ret = tps6594_i2c_reg_read_with_crc(client, page, reg + i, val_bytes + i);
return ret;
}
/* Write register: I2C address = I2C base address + Page index */
msgs[0].addr = client->addr + page;
msgs[0].flags = 0;
msgs[0].len = 1;
msgs[0].buf = &reg;
/* Read data */
msgs[1].addr = msgs[0].addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = val_size;
msgs[1].buf = val_bytes;
return tps6594_i2c_transfer(client->adapter, msgs, 2);
}
static int tps6594_i2c_write(void *context, const void *data, size_t count)
{
struct i2c_client *client = context;
struct tps6594 *tps = i2c_get_clientdata(client);
struct i2c_msg msg;
const u8 *bytes = data;
u8 *buf;
const u8 page = bytes[1];
const u8 reg = bytes[0];
int ret = 0;
int i;
if (tps->use_crc) {
/*
* Auto-increment feature does not support CRC protocol.
* Converts the bulk write operation into a series of single write operations.
*/
for (i = 0 ; ret == 0 && i < count - 2 ; i++)
ret = tps6594_i2c_reg_write_with_crc(client, page, reg + i, bytes[i + 2]);
return ret;
}
/* Setup buffer: page byte is not sent */
buf = kzalloc(--count, GFP_KERNEL);
if (!buf)
return -ENOMEM;
buf[0] = reg;
for (i = 0 ; i < count - 1 ; i++)
buf[i + 1] = bytes[i + 2];
/* Write register and data: I2C address = I2C base address + Page index */
msg.addr = client->addr + page;
msg.flags = client->flags & I2C_M_TEN;
msg.len = count;
msg.buf = buf;
ret = tps6594_i2c_transfer(client->adapter, &msg, 1);
kfree(buf);
return ret;
}
static const struct regmap_config tps6594_i2c_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = TPS6594_REG_DWD_FAIL_CNT_REG,
.volatile_reg = tps6594_is_volatile_reg,
.read = tps6594_i2c_read,
.write = tps6594_i2c_write,
};
static const struct of_device_id tps6594_i2c_of_match_table[] = {
{ .compatible = "ti,tps6594-q1", .data = (void *)TPS6594, },
{ .compatible = "ti,tps6593-q1", .data = (void *)TPS6593, },
{ .compatible = "ti,lp8764-q1", .data = (void *)LP8764, },
{}
};
MODULE_DEVICE_TABLE(of, tps6594_i2c_of_match_table);
static int tps6594_i2c_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct tps6594 *tps;
const struct of_device_id *match;
tps = devm_kzalloc(dev, sizeof(*tps), GFP_KERNEL);
if (!tps)
return -ENOMEM;
i2c_set_clientdata(client, tps);
tps->dev = dev;
tps->reg = client->addr;
tps->irq = client->irq;
tps->regmap = devm_regmap_init(dev, NULL, client, &tps6594_i2c_regmap_config);
if (IS_ERR(tps->regmap))
return dev_err_probe(dev, PTR_ERR(tps->regmap), "Failed to init regmap\n");
match = of_match_device(tps6594_i2c_of_match_table, dev);
if (!match)
return dev_err_probe(dev, PTR_ERR(match), "Failed to find matching chip ID\n");
tps->chip_id = (unsigned long)match->data;
crc8_populate_msb(tps6594_i2c_crc_table, TPS6594_CRC8_POLYNOMIAL);
return tps6594_device_init(tps, enable_crc);
}
static struct i2c_driver tps6594_i2c_driver = {
.driver = {
.name = "tps6594",
.of_match_table = tps6594_i2c_of_match_table,
},
.probe_new = tps6594_i2c_probe,
};
module_i2c_driver(tps6594_i2c_driver);
MODULE_AUTHOR("Julien Panis <jpanis@baylibre.com>");
MODULE_DESCRIPTION("TPS6594 I2C Interface Driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0
/*
* SPI access driver for TI TPS6594/TPS6593/LP8764 PMICs
*
* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
*/
#include <linux/crc8.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/mfd/tps6594.h>
#define TPS6594_SPI_PAGE_SHIFT 5
#define TPS6594_SPI_READ_BIT BIT(4)
static bool enable_crc;
module_param(enable_crc, bool, 0444);
MODULE_PARM_DESC(enable_crc, "Enable CRC feature for SPI interface");
DECLARE_CRC8_TABLE(tps6594_spi_crc_table);
static int tps6594_spi_reg_read(void *context, unsigned int reg, unsigned int *val)
{
struct spi_device *spi = context;
struct tps6594 *tps = spi_get_drvdata(spi);
u8 buf[4] = { 0 };
size_t count_rx = 1;
int ret;
buf[0] = reg;
buf[1] = TPS6594_REG_TO_PAGE(reg) << TPS6594_SPI_PAGE_SHIFT | TPS6594_SPI_READ_BIT;
if (tps->use_crc)
count_rx++;
ret = spi_write_then_read(spi, buf, 2, buf + 2, count_rx);
if (ret < 0)
return ret;
if (tps->use_crc && buf[3] != crc8(tps6594_spi_crc_table, buf, 3, CRC8_INIT_VALUE))
return -EIO;
*val = buf[2];
return 0;
}
static int tps6594_spi_reg_write(void *context, unsigned int reg, unsigned int val)
{
struct spi_device *spi = context;
struct tps6594 *tps = spi_get_drvdata(spi);
u8 buf[4] = { 0 };
size_t count = 3;
buf[0] = reg;
buf[1] = TPS6594_REG_TO_PAGE(reg) << TPS6594_SPI_PAGE_SHIFT;
buf[2] = val;
if (tps->use_crc)
buf[3] = crc8(tps6594_spi_crc_table, buf, count++, CRC8_INIT_VALUE);
return spi_write(spi, buf, count);
}
static const struct regmap_config tps6594_spi_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = TPS6594_REG_DWD_FAIL_CNT_REG,
.volatile_reg = tps6594_is_volatile_reg,
.reg_read = tps6594_spi_reg_read,
.reg_write = tps6594_spi_reg_write,
.use_single_read = true,
.use_single_write = true,
};
static const struct of_device_id tps6594_spi_of_match_table[] = {
{ .compatible = "ti,tps6594-q1", .data = (void *)TPS6594, },
{ .compatible = "ti,tps6593-q1", .data = (void *)TPS6593, },
{ .compatible = "ti,lp8764-q1", .data = (void *)LP8764, },
{}
};
MODULE_DEVICE_TABLE(of, tps6594_spi_of_match_table);
static int tps6594_spi_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct tps6594 *tps;
const struct of_device_id *match;
tps = devm_kzalloc(dev, sizeof(*tps), GFP_KERNEL);
if (!tps)
return -ENOMEM;
spi_set_drvdata(spi, tps);
tps->dev = dev;
tps->reg = spi->chip_select;
tps->irq = spi->irq;
tps->regmap = devm_regmap_init(dev, NULL, spi, &tps6594_spi_regmap_config);
if (IS_ERR(tps->regmap))
return dev_err_probe(dev, PTR_ERR(tps->regmap), "Failed to init regmap\n");
match = of_match_device(tps6594_spi_of_match_table, dev);
if (!match)
return dev_err_probe(dev, PTR_ERR(match), "Failed to find matching chip ID\n");
tps->chip_id = (unsigned long)match->data;
crc8_populate_msb(tps6594_spi_crc_table, TPS6594_CRC8_POLYNOMIAL);
return tps6594_device_init(tps, enable_crc);
}
static struct spi_driver tps6594_spi_driver = {
.driver = {
.name = "tps6594",
.of_match_table = tps6594_spi_of_match_table,
},
.probe = tps6594_spi_probe,
};
module_spi_driver(tps6594_spi_driver);
MODULE_AUTHOR("Julien Panis <jpanis@baylibre.com>");
MODULE_DESCRIPTION("TPS6594 SPI Interface Driver");
MODULE_LICENSE("GPL");

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