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ASoC: SOF: Intel: hda-stream: limit PROCEN workaround

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The work-around enabled in hda-stream.c is only required on earlier
versions of SOCs/PCH (Skylake, KabyLake, ApolloLake,
GeminiLake). Before setting the format on the host DMA, it is required
to couple the host and link DMA - which as a consequence shall use the
same format.

This patch introduces a quirk field in the platform descriptor and
makes the work-around conditional. Newer platforms have
no limitations on the use of host and link DMA, which can use
different formats.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Link: https://lore.kernel.org/r/20211207193947.71080-3-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Pierre-Louis Bossart 2021-12-07 13:39:42 -06:00 committed by Mark Brown
parent c697ef868f
commit a792bfc1c2
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
3 changed files with 17 additions and 6 deletions
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1
sound/soc/sof/intel/apl.c
View File

@ -147,5 +147,6 @@ const struct sof_intel_dsp_desc apl_chip_info = {
.rom_init_timeout = 150, .rom_init_timeout = 150,
.ssp_count = APL_SSP_COUNT, .ssp_count = APL_SSP_COUNT,
.ssp_base_offset = APL_SSP_BASE_OFFSET, .ssp_base_offset = APL_SSP_BASE_OFFSET,
.quirks = SOF_INTEL_PROCEN_FMT_QUIRK,
}; };
EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

18
sound/soc/sof/intel/hda-stream.c
View File

@ -472,6 +472,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
struct snd_dma_buffer *dmab, struct snd_dma_buffer *dmab,
struct snd_pcm_hw_params *params) struct snd_pcm_hw_params *params)
{ {
const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata);
struct hdac_bus *bus = sof_to_bus(sdev); struct hdac_bus *bus = sof_to_bus(sdev);
struct hdac_stream *hstream = &stream->hstream; struct hdac_stream *hstream = &stream->hstream;
int sd_offset = SOF_STREAM_SD_OFFSET(hstream); int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
@ -584,6 +585,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
/* /*
* Recommended hardware programming sequence for HDAudio DMA format * Recommended hardware programming sequence for HDAudio DMA format
* on earlier platforms - this is not needed on newer platforms
* *
* 1. Put DMA into coupled mode by clearing PPCTL.PROCEN bit * 1. Put DMA into coupled mode by clearing PPCTL.PROCEN bit
* for corresponding stream index before the time of writing * for corresponding stream index before the time of writing
@ -593,9 +595,11 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
* enable decoupled mode * enable decoupled mode
*/ */
/* couple host and link DMA, disable DSP features */ if (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK) {
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, /* couple host and link DMA, disable DSP features */
mask, 0); snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
mask, 0);
}
/* program stream format */ /* program stream format */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
@ -603,9 +607,11 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
SOF_HDA_ADSP_REG_CL_SD_FORMAT, SOF_HDA_ADSP_REG_CL_SD_FORMAT,
0xffff, hstream->format_val); 0xffff, hstream->format_val);
/* decouple host and link DMA, enable DSP features */ if (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK) {
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, /* decouple host and link DMA, enable DSP features */
mask, mask); snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
mask, mask);
}
/* program last valid index */ /* program last valid index */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,

4
sound/soc/sof/intel/shim.h
View File

@ -151,6 +151,9 @@
#define PCI_PMCS 0x84 #define PCI_PMCS 0x84
#define PCI_PMCS_PS_MASK 0x3 #define PCI_PMCS_PS_MASK 0x3
/* Intel quirks */
#define SOF_INTEL_PROCEN_FMT_QUIRK BIT(0)
/* DSP hardware descriptor */ /* DSP hardware descriptor */
struct sof_intel_dsp_desc { struct sof_intel_dsp_desc {
int cores_num; int cores_num;
@ -166,6 +169,7 @@ struct sof_intel_dsp_desc {
int ssp_base_offset; /* base address of the SSPs */ int ssp_base_offset; /* base address of the SSPs */
u32 sdw_shim_base; u32 sdw_shim_base;
u32 sdw_alh_base; u32 sdw_alh_base;
u32 quirks;
bool (*check_sdw_irq)(struct snd_sof_dev *sdev); bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
}; };