Qualcomm ARM32 DeviceTree updates for v6.4

stdout-path is defined for the ALFA Network AP120C-AC, to avoid the need
 to pass this information on the kernel commandline. Ath10k is wired up
 to read calibration data from the "ART" partition.
 
 PCI I/O port ranges are fixed on IPQ4019 and IPQ8064.
 
 Supply clocks are defined for KPSS L2CC and ACC clock controllers.
 
 Supply clocks for the global clock controller are being specified on
 IPQ4019, MSM8974 and MSM8226.
 
 PCIe RC support is enabled on the SDX55 T55 development board, IPA is
 defined for the SDX55 and a number of cleanup patches are introduced.
 
 Compatibles for QRB2210/QCM2290, IPQ9574, QRD8550 and IPQ5332 platforms
 are added, and the RB1, Yiming LTE dongle, Xiaomi Mi A3, MI01.2 and
 MI01.6 boards.
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Merge tag 'qcom-dts-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm ARM32 DeviceTree updates for v6.4

stdout-path is defined for the ALFA Network AP120C-AC, to avoid the need
to pass this information on the kernel commandline. Ath10k is wired up
to read calibration data from the "ART" partition.

PCI I/O port ranges are fixed on IPQ4019 and IPQ8064.

Supply clocks are defined for KPSS L2CC and ACC clock controllers.

Supply clocks for the global clock controller are being specified on
IPQ4019, MSM8974 and MSM8226.

PCIe RC support is enabled on the SDX55 T55 development board, IPA is
defined for the SDX55 and a number of cleanup patches are introduced.

Compatibles for QRB2210/QCM2290, IPQ9574, QRD8550 and IPQ5332 platforms
are added, and the RB1, Yiming LTE dongle, Xiaomi Mi A3, MI01.2 and
MI01.6 boards.

* tag 'qcom-dts-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (28 commits)
  dt-bindings: arm: qcom: Add Yiming LTE dongle uz801-v3.0 (yiming-uz801v3)
  dt-bindings: vendor-prefixes: Add Henan Yiming Technology Co., Ltd.
  ARM: dts: qcom: sdx55: add dedicated SDX55 TCSR compatible
  ARM: dts: qcom: sdx55-t55: Move "status" property down
  ARM: dts: qcom: sdx55-t55: Enable PCIe RC support
  ARM: dts: qcom: sdx55: List the property values vertically
  ARM: dts: qcom: sdx55: Add support for PCIe RC controller
  ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane}
  ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node
  ARM: dts: qcom: ipq8064: Fix the PCI I/O port range
  ARM: dts: qcom: ipq4019: Fix the PCI I/O port range
  ARM: dts: qcom: apq8064: Use 0x prefix for the PCI I/O and MEM ranges
  dt-bindings: arm: qcom: Add ipq9574 compatible
  ARM: dts: qcom: msm8974: add correct XO clock source to GCC node
  ARM: dts: qcom: msm8226: add clocks and clock-names to GCC node
  ARM: dts: qcom: rename kpss-acc-v2 nodes to power-manager nodes
  ARM: dts: qcom: add missing clock configuration for kpss-acc-v1
  ARM: dts: qcom: add and fix clock configuration for kpss-gcc nodes
  ARM: dts: qcom: add per SoC compatible for qcom,kpss-gcc nodes
  dt-bindings: qcom: add ipq5332 boards
  ...

Link: https://lore.kernel.org/r/20230410155226.5127-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-04-14 17:52:32 +02:00
commit a8127d2aae
15 changed files with 304 additions and 80 deletions

@ -30,8 +30,10 @@ description: |
apq8084
apq8096
ipq4018
ipq5332
ipq6018
ipq8074
ipq9574
mdm9615
msm8226
msm8916
@ -80,6 +82,8 @@ description: |
The 'board' element must be one of the following strings:
adp
ap-al02-c7
ap-mi01.2
cdp
cp01-c1
dragonboard
@ -226,6 +230,7 @@ properties:
- thwc,uf896
- thwc,ufi001c
- wingtech,wt88047
- yiming,uz801-v3
- const: qcom,msm8916
- items:
@ -320,6 +325,11 @@ properties:
- qcom,ipq4019-dk04.1-c1
- const: qcom,ipq4019
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
- const: qcom,ipq5332
- items:
- enum:
- mikrotik,rb3011
@ -333,6 +343,11 @@ properties:
- qcom,ipq8074-hk10-c2
- const: qcom,ipq8074
- items:
- enum:
- qcom,ipq9574-ap-al02-c7
- const: qcom,ipq9574
- description: Sierra Wireless MangOH Green with WP8548 Module
items:
- const: swir,mangoh-green-wp8548
@ -913,6 +928,7 @@ properties:
- items:
- enum:
- qcom,sm8550-mtp
- qcom,sm8550-qrd
- const: qcom,sm8550
# Board compatibles go above

@ -1538,6 +1538,8 @@ patternProperties:
description: Yes Optoelectronics Co.,Ltd.
"^yic,.*":
description: YIC System Co., Ltd.
"^yiming,.*":
description: Henan Yiming Technology Co., Ltd.
"^ylm,.*":
description: Shenzhen Yangliming Electronic Technology Co., Ltd.
"^yna,.*":

@ -388,21 +388,37 @@
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu0_aux";
#clock-cells = <0>;
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu1_aux";
#clock-cells = <0>;
};
acc2: clock-controller@20a8000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu2_aux";
#clock-cells = <0>;
};
acc3: clock-controller@20b8000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu3_aux";
#clock-cells = <0>;
};
saw0: power-controller@2089000 {
@ -879,8 +895,11 @@
};
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc", "syscon";
compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
#clock-cells = <0>;
};
rpm: rpm@108000 {
@ -1260,7 +1279,7 @@
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-320000000 {
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
};
@ -1494,8 +1513,8 @@
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */
<0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */
ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
<0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;

@ -654,25 +654,25 @@
regulator;
};
acc0: clock-controller@f9088000 {
acc0: power-manager@f9088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9088000 0x1000>,
<0xf9008000 0x1000>;
};
acc1: clock-controller@f9098000 {
acc1: power-manager@f9098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9098000 0x1000>,
<0xf9008000 0x1000>;
};
acc2: clock-controller@f90a8000 {
acc2: power-manager@f90a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90a8000 0x1000>,
<0xf9008000 0x1000>;
};
acc3: clock-controller@f90b8000 {
acc3: power-manager@f90b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90b8000 0x1000>,
<0xf9008000 0x1000>;

@ -8,6 +8,14 @@
model = "ALFA Network AP120C-AC";
compatible = "alfa-network,ap120c-ac", "qcom,ipq4018";
aliases {
serial0 = &blsp1_uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
@ -68,7 +76,7 @@
};
};
usb-power {
usb-power-hog {
line-name = "USB-power";
gpios = <1 GPIO_ACTIVE_HIGH>;
gpio-hog;
@ -162,6 +170,17 @@
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
partition@180000 {
@ -178,7 +197,7 @@
};
};
nand@1 {
flash@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <40000000>;
@ -225,10 +244,14 @@
&wifi0 {
status = "okay";
nvmem-cell-names = "pre-calibration";
nvmem-cells = <&precal_art_1000>;
};
&wifi1 {
status = "okay";
nvmem-cell-names = "pre-calibration";
nvmem-cells = <&precal_art_5000>;
qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
};

@ -143,7 +143,6 @@
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-output-names = "gcc_sleep_clk_src";
#clock-cells = <0>;
};
@ -190,6 +189,8 @@
#power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x1800000 0x60000>;
clocks = <&xo>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";
};
prng: rng@22000 {
@ -325,22 +326,22 @@
status = "disabled";
};
acc0: clock-controller@b088000 {
acc0: power-manager@b088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
};
acc1: clock-controller@b098000 {
acc1: power-manager@b098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
};
acc2: clock-controller@b0a8000 {
acc2: power-manager@b0a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
};
acc3: clock-controller@b0b8000 {
acc3: power-manager@b0b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
};
@ -426,8 +427,8 @@
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
<0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,
<0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";

@ -569,16 +569,20 @@
};
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc", "syscon";
compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
reg = <0x02011000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu_l2_aux";
#clock-cells = <0>;
};
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu0_aux";
#clock-cells = <0>;
};
saw0: regulator@2089000 {
@ -590,6 +594,10 @@
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu1_aux";
#clock-cells = <0>;
};
saw1: regulator@2099000 {
@ -1081,8 +1089,8 @@
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */
0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@ -1132,8 +1140,8 @@
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */
0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@ -1183,8 +1191,8 @@
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */
0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";

@ -116,7 +116,7 @@
};
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc", "syscon";
compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
reg = <0x02011000 0x1000>;
};

@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,gcc-msm8974.h>
@ -377,6 +378,11 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>;
clock-names = "xo",
"sleep_clk";
};
mmcc: clock-controller@fd8c0000 {

@ -473,7 +473,7 @@
};
l2cc: clock-controller@2082000 {
compatible = "qcom,kpss-gcc", "syscon";
compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon";
reg = <0x02082000 0x1000>;
};

@ -182,8 +182,11 @@
};
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc", "syscon";
compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
#clock-cells = <0>;
};
rpm: rpm@108000 {
@ -204,11 +207,19 @@
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu0_aux";
#clock-cells = <0>;
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu1_aux";
#clock-cells = <0>;
};
saw0: regulator@2089000 {

@ -418,22 +418,22 @@
regulator;
};
acc0: clock-controller@f9088000 {
acc0: power-manager@f9088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
};
acc1: clock-controller@f9098000 {
acc1: power-manager@f9098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
};
acc2: clock-controller@f90a8000 {
acc2: power-manager@f90a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
};
acc3: clock-controller@f90b8000 {
acc3: power-manager@f90b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
};
@ -1057,7 +1057,7 @@
#power-domain-cells = <1>;
reg = <0xfc400000 0x4000>;
clocks = <&xo_board>,
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>;
clock-names = "xo",
"sleep_clk";

@ -242,6 +242,23 @@
status = "okay";
};
&pcie_phy {
vdda-phy-supply = <&vreg_l1e_bb_1p2>;
vdda-pll-supply = <&vreg_l4e_bb_0p875>;
status = "okay";
};
&pcie_rc {
perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie_default>;
pinctrl-names = "default";
status = "okay";
};
&qpic_bam {
status = "okay";
};
@ -261,21 +278,48 @@
};
&remoteproc_mpss {
status = "okay";
memory-region = <&mpss_adsp_mem>;
status = "okay";
};
&tlmm {
pcie_default: pcie-default-state {
clkreq-pins {
pins = "gpio56";
function = "pcie_clkreq";
drive-strength = <2>;
bias-pull-up;
};
perst-pins {
pins = "gpio57";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
wake-pins {
pins = "gpio53";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&usb_hsphy {
status = "okay";
vdda-pll-supply = <&vreg_l4e_bb_0p875>;
vdda33-supply = <&vreg_l10e_3p1>;
vdda18-supply = <&vreg_l5e_bb_1p7>;
status = "okay";
};
&usb_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l4e_bb_0p875>;
vdda-pll-supply = <&vreg_l1e_bb_1p2>;
status = "okay";
};
&usb {

@ -242,7 +242,7 @@
status = "okay";
};
&pcie0_phy {
&pcie_phy {
status = "okay";
vdda-phy-supply = <&vreg_l1e_bb_1p2>;

@ -304,7 +304,137 @@
status = "disabled";
};
pcie0_phy: phy@1c07000 {
pcie_rc: pcie@1c00000 {
compatible = "qcom,pcie-sdx55";
reg = <0x01c00000 0x3000>,
<0x40000000 0xf1d>,
<0x40000f20 0xc8>,
<0x40001000 0x1000>,
<0x40100000 0x100000>;
reg-names = "parf",
"dbi",
"elbi",
"atu",
"config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7",
"msi8";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_PIPE_CLK>,
<&gcc GCC_PCIE_AUX_CLK>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_SLV_AXI_CLK>,
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_SLEEP_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"sleep";
assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
<0x100 &apps_smmu 0x0201 0x1>,
<0x200 &apps_smmu 0x0202 0x1>,
<0x300 &apps_smmu 0x0203 0x1>,
<0x400 &apps_smmu 0x0204 0x1>;
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "pci";
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie_lane>;
phy-names = "pciephy";
status = "disabled";
};
pcie_ep: pcie-ep@1c00000 {
compatible = "qcom,sdx55-pcie-ep";
reg = <0x01c00000 0x3000>,
<0x40000000 0xf1d>,
<0x40000f20 0xc8>,
<0x40001000 0x1000>,
<0x40200000 0x100000>,
<0x01c03000 0x3000>;
reg-names = "parf",
"dbi",
"elbi",
"atu",
"addr_space",
"mmio";
qcom,perst-regs = <&tcsr 0xb258 0xb270>;
clocks = <&gcc GCC_PCIE_AUX_CLK>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_SLV_AXI_CLK>,
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_SLEEP_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>;
clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"sleep",
"ref";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global",
"doorbell";
reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "core";
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie_lane>;
phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
status = "disabled";
};
pcie_phy: phy@1c07000 {
compatible = "qcom,sdx55-qmp-pcie-phy";
reg = <0x01c07000 0x1c4>;
#address-cells = <1>;
@ -314,7 +444,10 @@
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
<&gcc GCC_PCIE_RCHNG_PHY_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen";
resets = <&gcc GCC_PCIE_PHY_BCR>;
reset-names = "phy";
@ -324,7 +457,7 @@
status = "disabled";
pcie0_lane: lanes@1c06000 {
pcie_lane: lanes@1c06000 {
reg = <0x01c06000 0x104>, /* tx0 */
<0x01c06200 0x328>, /* rx0 */
<0x01c07200 0x1e8>, /* pcs */
@ -385,7 +518,7 @@
};
tcsr: syscon@1fcb000 {
compatible = "syscon";
compatible = "qcom,sdx55-tcsr", "syscon";
reg = <0x01fc0000 0x1000>;
};
@ -401,45 +534,6 @@
status = "disabled";
};
pcie_ep: pcie-ep@40000000 {
compatible = "qcom,sdx55-pcie-ep";
reg = <0x01c00000 0x3000>,
<0x40000000 0xf1d>,
<0x40000f20 0xc8>,
<0x40001000 0x1000>,
<0x40200000 0x100000>,
<0x01c03000 0x3000>;
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
"mmio";
qcom,perst-regs = <&tcsr 0xb258 0xb270>;
clocks = <&gcc GCC_PCIE_AUX_CLK>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_SLV_AXI_CLK>,
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_SLEEP_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>;
clock-names = "aux", "cfg", "bus_master", "bus_slave",
"slave_q2a", "sleep", "ref";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global", "doorbell";
reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "core";
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie0_lane>;
phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
status = "disabled";
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sdx55-mpss-pas";
reg = <0x04080000 0x4040>;