[POWERPC] ppc: Add support for AMCC Taishan 440GX eval board
This patch adds support for the AMCC Taishan PPC440GX evaluation board. This is still an arch/ppc port. I'm aware that the move of 4xx to arch/powerpc is making good progress right now. So this patch is mainly intended to make the Taishan support available for the community right now. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Stefan Roese
Paul Mackerras
parent
7ac9a13717
commit
ab9367e38f
1077
arch/ppc/configs/taishan_defconfig
Normal file
1077
arch/ppc/configs/taishan_defconfig
Normal file
File diff suppressed because it is too large
Load Diff
@ -98,6 +98,12 @@ config OCOTEA
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help
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This option enables support for the IBM PPC440GX evaluation board.
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config TAISHAN
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bool "Taishan"
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select WANT_EARLY_SERIAL
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help
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This option enables support for the AMCC PPC440GX evaluation board.
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endchoice
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config EP405PC
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@ -126,7 +132,7 @@ config 440GP
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config 440GX
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bool
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depends on OCOTEA
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depends on OCOTEA || TAISHAN
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default y
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config 440SP
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@ -173,7 +179,7 @@ config BOOKE
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config IBM_OCP
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bool
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depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
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depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || TAISHAN || WALNUT
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default y
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config IBM_EMAC4
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@ -12,6 +12,7 @@ obj-$(CONFIG_OCOTEA) += ocotea.o
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obj-$(CONFIG_REDWOOD_5) += redwood5.o
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obj-$(CONFIG_REDWOOD_6) += redwood6.o
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obj-$(CONFIG_SYCAMORE) += sycamore.o
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obj-$(CONFIG_TAISHAN) += taishan.o
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obj-$(CONFIG_WALNUT) += walnut.o
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obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o
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obj-$(CONFIG_XILINX_ML403) += xilinx_ml403.o
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395
arch/ppc/platforms/4xx/taishan.c
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395
arch/ppc/platforms/4xx/taishan.c
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@ -0,0 +1,395 @@
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/*
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* arch/ppc/platforms/4xx/taishan.c
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*
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* AMCC Taishan board specific routines
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*
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* Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/types.h>
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#include <linux/major.h>
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#include <linux/blkdev.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/ide.h>
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#include <linux/initrd.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/tty.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/ndfc.h>
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#include <linux/mtd/physmap.h>
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#include <asm/machdep.h>
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#include <asm/ocp.h>
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#include <asm/bootinfo.h>
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#include <asm/ppcboot.h>
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#include <syslib/gen550.h>
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#include <syslib/ibm440gx_common.h>
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extern bd_t __res;
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static struct ibm44x_clocks clocks __initdata;
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/*
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* NOR FLASH configuration (using mtd physmap driver)
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*/
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/* start will be added dynamically, end is always fixed */
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static struct resource taishan_nor_resource = {
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.start = TAISHAN_FLASH_ADDR,
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.end = 0x1ffffffffULL,
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.flags = IORESOURCE_MEM,
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};
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#define RW_PART0_OF 0
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#define RW_PART0_SZ 0x180000
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#define RW_PART1_SZ 0x200000
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/* Partition 2 will be autosized dynamically... */
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#define RW_PART3_SZ 0x80000
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#define RW_PART4_SZ 0x40000
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static struct mtd_partition taishan_nor_parts[] = {
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{
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.name = "kernel",
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.offset = 0,
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.size = RW_PART0_SZ
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},
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{
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.name = "root",
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.offset = MTDPART_OFS_APPEND,
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.size = RW_PART1_SZ,
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},
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{
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.name = "user",
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.offset = MTDPART_OFS_APPEND,
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/* .size = RW_PART2_SZ */ /* will be adjusted dynamically */
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},
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{
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.name = "env",
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.offset = MTDPART_OFS_APPEND,
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.size = RW_PART3_SZ,
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},
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{
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.name = "u-boot",
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.offset = MTDPART_OFS_APPEND,
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.size = RW_PART4_SZ,
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}
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};
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static struct physmap_flash_data taishan_nor_data = {
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.width = 4,
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.parts = taishan_nor_parts,
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.nr_parts = ARRAY_SIZE(taishan_nor_parts),
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};
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static struct platform_device taishan_nor_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &taishan_nor_data,
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},
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.num_resources = 1,
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.resource = &taishan_nor_resource,
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};
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static int taishan_setup_flash(void)
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{
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/*
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* Adjust partition 2 to flash size
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*/
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taishan_nor_parts[2].size = __res.bi_flashsize -
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RW_PART0_SZ - RW_PART1_SZ - RW_PART3_SZ - RW_PART4_SZ;
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platform_device_register(&taishan_nor_device);
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return 0;
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}
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arch_initcall(taishan_setup_flash);
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static void __init
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taishan_calibrate_decr(void)
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{
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unsigned int freq;
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if (mfspr(SPRN_CCR1) & CCR1_TCS)
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freq = TAISHAN_TMR_CLK;
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else
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freq = clocks.cpu;
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ibm44x_calibrate_decr(freq);
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}
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static int
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taishan_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "vendor\t\t: AMCC\n");
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seq_printf(m, "machine\t\t: PPC440GX EVB (Taishan)\n");
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ibm440gx_show_cpuinfo(m);
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return 0;
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}
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static inline int
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taishan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 23, 24, 25, 26 }, /* IDSEL 1 - PCI Slot 0 */
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{ 24, 25, 26, 23 }, /* IDSEL 2 - PCI Slot 1 */
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};
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const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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static void __init taishan_set_emacdata(void)
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{
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struct ocp_def *def;
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struct ocp_func_emac_data *emacdata;
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int i;
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/* Set phy_map, phy_mode, and mac_addr for each EMAC */
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for (i=2; i<4; i++) {
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def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
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emacdata = def->additions;
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if (i < 2) {
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emacdata->phy_map = 0x00000001; /* Skip 0x00 */
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emacdata->phy_mode = PHY_MODE_SMII;
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} else {
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emacdata->phy_map = 0x00000001; /* Skip 0x00 */
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emacdata->phy_mode = PHY_MODE_RGMII;
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}
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if (i == 0)
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memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
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else if (i == 1)
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memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
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else if (i == 2)
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memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
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else if (i == 3)
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memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
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}
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}
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#define PCIX_READW(offset) \
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(readw(pcix_reg_base+offset))
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#define PCIX_WRITEW(value, offset) \
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(writew(value, pcix_reg_base+offset))
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#define PCIX_WRITEL(value, offset) \
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(writel(value, pcix_reg_base+offset))
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/*
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* FIXME: This is only here to "make it work". This will move
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* to a ibm_pcix.c which will contain a generic IBM PCIX bridge
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* configuration library. -Matt
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*/
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static void __init
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taishan_setup_pcix(void)
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{
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void *pcix_reg_base;
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pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
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/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
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PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
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/* Disable all windows */
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PCIX_WRITEL(0, PCIX0_POM0SA);
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PCIX_WRITEL(0, PCIX0_POM1SA);
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PCIX_WRITEL(0, PCIX0_POM2SA);
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PCIX_WRITEL(0, PCIX0_PIM0SA);
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PCIX_WRITEL(0, PCIX0_PIM0SAH);
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PCIX_WRITEL(0, PCIX0_PIM1SA);
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PCIX_WRITEL(0, PCIX0_PIM2SA);
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PCIX_WRITEL(0, PCIX0_PIM2SAH);
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/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
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PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
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PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
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PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
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PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
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PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
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/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
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PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
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PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
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PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
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PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
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iounmap(pcix_reg_base);
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eieio();
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}
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static void __init
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taishan_setup_hose(void)
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{
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struct pci_controller *hose;
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/* Configure windows on the PCI-X host bridge */
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taishan_setup_pcix();
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hose = pcibios_alloc_controller();
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if (!hose)
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return;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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hose->pci_mem_offset = TAISHAN_PCI_MEM_OFFSET;
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pci_init_resource(&hose->io_resource,
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TAISHAN_PCI_LOWER_IO,
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TAISHAN_PCI_UPPER_IO,
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IORESOURCE_IO,
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"PCI host bridge");
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pci_init_resource(&hose->mem_resources[0],
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TAISHAN_PCI_LOWER_MEM,
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TAISHAN_PCI_UPPER_MEM,
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IORESOURCE_MEM,
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"PCI host bridge");
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hose->io_space.start = TAISHAN_PCI_LOWER_IO;
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hose->io_space.end = TAISHAN_PCI_UPPER_IO;
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hose->mem_space.start = TAISHAN_PCI_LOWER_MEM;
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hose->mem_space.end = TAISHAN_PCI_UPPER_MEM;
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hose->io_base_virt = ioremap64(TAISHAN_PCI_IO_BASE, TAISHAN_PCI_IO_SIZE);
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isa_io_base = (unsigned long) hose->io_base_virt;
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setup_indirect_pci(hose,
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TAISHAN_PCI_CFGA_PLB32,
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TAISHAN_PCI_CFGD_PLB32);
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hose->set_cfg_type = 1;
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hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = taishan_map_irq;
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}
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static void __init
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taishan_early_serial_map(void)
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{
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struct uart_port port;
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/* Setup ioremapped serial port access */
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memset(&port, 0, sizeof(port));
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port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
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port.irq = UART0_INT;
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port.uartclk = clocks.uart0;
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port.regshift = 0;
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port.iotype = UPIO_MEM;
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port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
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port.line = 0;
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if (early_serial_setup(&port) != 0)
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printk("Early serial init of port 0 failed\n");
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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/* Configure debug serial access */
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gen550_init(0, &port);
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/* Purge TLB entry added in head_44x.S for early serial access */
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_tlbie(UART0_IO_BASE);
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#endif
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port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
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port.irq = UART1_INT;
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port.uartclk = clocks.uart1;
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port.line = 1;
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if (early_serial_setup(&port) != 0)
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printk("Early serial init of port 1 failed\n");
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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/* Configure debug serial access */
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gen550_init(1, &port);
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#endif
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}
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static void __init
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taishan_setup_arch(void)
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{
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taishan_set_emacdata();
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ibm440gx_tah_enable();
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/*
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* Determine various clocks.
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* To be completely correct we should get SysClk
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* from FPGA, because it can be changed by on-board switches
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* --ebs
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*/
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ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
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ocp_sys_info.opb_bus_freq = clocks.opb;
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000/HZ;
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/* Setup PCI host bridge */
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taishan_setup_hose();
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_HDA1;
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#endif
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taishan_early_serial_map();
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/* Identify the system */
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printk("AMCC PowerPC 440GX Taishan Platform\n");
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}
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static void __init taishan_init(void)
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{
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ibm440gx_l2c_setup(&clocks);
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}
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void __init platform_init(unsigned long r3, unsigned long r4,
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unsigned long r5, unsigned long r6, unsigned long r7)
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{
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ibm44x_platform_init(r3, r4, r5, r6, r7);
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ppc_md.setup_arch = taishan_setup_arch;
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ppc_md.show_cpuinfo = taishan_show_cpuinfo;
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ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
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ppc_md.calibrate_decr = taishan_calibrate_decr;
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#ifdef CONFIG_KGDB
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ppc_md.early_serial_map = taishan_early_serial_map;
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#endif
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ppc_md.init = taishan_init;
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}
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67
arch/ppc/platforms/4xx/taishan.h
Normal file
67
arch/ppc/platforms/4xx/taishan.h
Normal file
@ -0,0 +1,67 @@
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/*
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* arch/ppc/platforms/4xx/taishan.h
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*
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* AMCC Taishan board definitions
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*
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* Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#ifndef __ASM_TAISHAN_H__
|
||||
#define __ASM_TAISHAN_H__
|
||||
|
||||
#include <platforms/4xx/ibm440gx.h>
|
||||
|
||||
/* External timer clock frequency */
|
||||
#define TAISHAN_TMR_CLK 25000000
|
||||
|
||||
/* Flash */
|
||||
#define TAISHAN_FPGA_ADDR 0x0000000141000000ULL
|
||||
#define TAISHAN_LCM_ADDR 0x0000000142000000ULL
|
||||
#define TAISHAN_FLASH_ADDR 0x00000001fc000000ULL
|
||||
#define TAISHAN_FLASH_SIZE 0x4000000
|
||||
|
||||
/*
|
||||
* Serial port defines
|
||||
*/
|
||||
#define RS_TABLE_SIZE 2
|
||||
|
||||
/* head_44x.S created UART mapping, used before early_serial_setup.
|
||||
* We cannot use default OpenBIOS UART mappings because they
|
||||
* don't work for configurations with more than 512M RAM. --ebs
|
||||
*/
|
||||
#define UART0_IO_BASE 0xF0000200
|
||||
#define UART1_IO_BASE 0xF0000300
|
||||
|
||||
#define BASE_BAUD 11059200/16
|
||||
#define STD_UART_OP(num) \
|
||||
{ 0, BASE_BAUD, 0, UART##num##_INT, \
|
||||
(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
|
||||
iomem_base: (void*)UART##num##_IO_BASE, \
|
||||
io_type: SERIAL_IO_MEM},
|
||||
|
||||
#define SERIAL_PORT_DFNS \
|
||||
STD_UART_OP(0) \
|
||||
STD_UART_OP(1)
|
||||
|
||||
/* PCI support */
|
||||
#define TAISHAN_PCI_LOWER_IO 0x00000000
|
||||
#define TAISHAN_PCI_UPPER_IO 0x0000ffff
|
||||
#define TAISHAN_PCI_LOWER_MEM 0x80000000
|
||||
#define TAISHAN_PCI_UPPER_MEM 0xffffefff
|
||||
|
||||
#define TAISHAN_PCI_CFGA_PLB32 0x0ec00000
|
||||
#define TAISHAN_PCI_CFGD_PLB32 0x0ec00004
|
||||
|
||||
#define TAISHAN_PCI_IO_BASE 0x0000000208000000ULL
|
||||
#define TAISHAN_PCI_IO_SIZE 0x00010000
|
||||
#define TAISHAN_PCI_MEM_OFFSET 0x00000000
|
||||
|
||||
#endif /* __ASM_TAISHAN_H__ */
|
||||
#endif /* __KERNEL__ */
|
||||
@ -69,6 +69,7 @@ obj-$(CONFIG_SANDPOINT) += pci_auto.o todc_time.o
|
||||
obj-$(CONFIG_SBC82xx) += todc_time.o
|
||||
obj-$(CONFIG_SPRUCE) += cpc700_pic.o pci_auto.o \
|
||||
todc_time.o
|
||||
obj-$(CONFIG_TAISHAN) += pci_auto.o
|
||||
obj-$(CONFIG_8260) += m8260_setup.o pq2_devices.o pq2_sys.o \
|
||||
ppc_sys.o
|
||||
obj-$(CONFIG_PCI_8260) += m82xx_pci.o pci_auto.o
|
||||
|
||||
@ -109,6 +109,10 @@ void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
#include <platforms/4xx/ocotea.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TAISHAN)
|
||||
#include <platforms/4xx/taishan.h>
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef CONFIG_40x
|
||||
/*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user