MIPS: math-emu: Always propagate sNaN payload in quieting
Propagate sNaN payload in quieting in the legacy-NaN mode as well. If clearing the quiet bit would produce infinity, then set the next lower trailing significand field bit, matching the SB-1 and BMIPS5000 hardware implementations. Some other MIPS FPU hardware implementations do produce the default qNaN bit pattern instead. This reverts some changes made for semantics preservation with commit dc3ddf42 [MIPS: math-emu: Update sNaN quieting handlers], consequently bringing back most of the semantics from before commit fdffbafb [Lots of FPU bug fixes from Kjeld Borch Egevang.], except from the qNaN produced in the infinity case. Previously the default qNaN bit pattern was produced in that case. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -54,10 +54,13 @@ union ieee754dp __cold ieee754dp_nanxcpt(union ieee754dp r)
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assert(ieee754dp_issnan(r));
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ieee754_setcx(IEEE754_INVALID_OPERATION);
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if (ieee754_csr.nan2008)
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if (ieee754_csr.nan2008) {
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DPMANT(r) |= DP_MBIT(DP_FBITS - 1);
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else
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r = ieee754dp_indef();
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} else {
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DPMANT(r) &= ~DP_MBIT(DP_FBITS - 1);
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if (!ieee754dp_isnan(r))
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DPMANT(r) |= DP_MBIT(DP_FBITS - 2);
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}
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return r;
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}
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@ -54,10 +54,13 @@ union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp r)
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assert(ieee754sp_issnan(r));
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ieee754_setcx(IEEE754_INVALID_OPERATION);
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if (ieee754_csr.nan2008)
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if (ieee754_csr.nan2008) {
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SPMANT(r) |= SP_MBIT(SP_FBITS - 1);
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else
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r = ieee754sp_indef();
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} else {
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SPMANT(r) &= ~SP_MBIT(SP_FBITS - 1);
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if (!ieee754sp_isnan(r))
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SPMANT(r) |= SP_MBIT(SP_FBITS - 2);
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}
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return r;
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}
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