iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clk: qcom: gcc-msm8996: drop unsupported clock sources

Browse Source 
In preparation of updating the msm8996 gcc driver, drop all unsupported
GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3).
Downstream kernel also does not provide support for these GPLL sources,
so it is safe to drop them.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-14-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov
2021-12-28 07:54:12 +03:00
committed by Bjorn Andersson
parent ed96df3d46
commit b554a687b4
1 changed files with 6 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

55
drivers/clk/qcom/gcc-msm8996.c
View File

@ -27,15 +27,10 @@
enum {
P_XO,
P_GPLL0,
P_GPLL2,
P_GPLL3,
P_GPLL1,
P_GPLL2_EARLY,
P_GPLL0_EARLY_DIV,
P_SLEEP_CLK,
P_GPLL4,
P_AUD_REF_CLK,
P_GPLL1_EARLY_DIV
};
static const struct parent_map gcc_sleep_clk_map[] = {
@ -130,44 +125,6 @@ static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
"gpll0_early_div"
};
static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1_EARLY_DIV, 3 },
{ P_GPLL1, 4 },
{ P_GPLL4, 5 },
{ P_GPLL0_EARLY_DIV, 6 }
};
static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
"xo",
"gpll0",
"gpll1_early_div",
"gpll1",
"gpll4",
"gpll0_early_div"
};
static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
{ P_GPLL3, 3 },
{ P_GPLL1, 4 },
{ P_GPLL2_EARLY, 5 },
{ P_GPLL0_EARLY_DIV, 6 }
};
static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
"xo",
"gpll0",
"gpll2",
"gpll3",
"gpll1",
"gpll2_early",
"gpll0_early_div"
};
static struct clk_fixed_factor xo = {
.mult = 1,
.div = 1,
@ -285,12 +242,12 @@ static const struct freq_tbl ftbl_system_noc_clk_src[] = {
static struct clk_rcg2 system_noc_clk_src = {
.cmd_rcgr = 0x0401c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
.freq_tbl = ftbl_system_noc_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_clk_src",
.parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div),
.parent_names = gcc_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
@ -1257,12 +1214,12 @@ static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
static struct clk_rcg2 qspi_ser_clk_src = {
.cmd_rcgr = 0x8b00c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
.parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
.freq_tbl = ftbl_qspi_ser_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "qspi_ser_clk_src",
.parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div),
.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};