x86/coco: Add API to handle encryption mask
AMD SME/SEV uses a bit in the page table entries to indicate that the page is encrypted and not accessible to the VMM. TDX uses a similar approach, but the polarity of the mask is opposite to AMD: if the bit is set the page is accessible to VMM. Provide vendor-neutral API to deal with the mask: cc_mkenc() and cc_mkdec() modify given address to make it encrypted/decrypted. It can be applied to phys_addr_t, pgprotval_t or page table entry value. pgprot_encrypted() and pgprot_decrypted() reimplemented using new helpers. The implementation will be extended to cover TDX. pgprot_decrypted() is used by drivers (i915, virtio_gpu, vfio). cc_mkdec() called by pgprot_decrypted(). Export cc_mkdec(). Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20220222185740.26228-5-kirill.shutemov@linux.intel.com
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@ -14,6 +14,7 @@
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#include <asm/processor.h>
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static enum cc_vendor vendor __ro_after_init;
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static u64 cc_mask __ro_after_init;
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static bool intel_cc_platform_has(enum cc_attr attr)
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{
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@ -84,7 +85,33 @@ bool cc_platform_has(enum cc_attr attr)
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}
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EXPORT_SYMBOL_GPL(cc_platform_has);
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u64 cc_mkenc(u64 val)
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{
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switch (vendor) {
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case CC_VENDOR_AMD:
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return val | cc_mask;
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default:
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return val;
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}
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}
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u64 cc_mkdec(u64 val)
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{
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switch (vendor) {
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case CC_VENDOR_AMD:
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return val & ~cc_mask;
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default:
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return val;
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}
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}
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EXPORT_SYMBOL_GPL(cc_mkdec);
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__init void cc_set_vendor(enum cc_vendor v)
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{
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vendor = v;
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}
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__init void cc_set_mask(u64 mask)
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{
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cc_mask = mask;
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}
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@ -2,6 +2,8 @@
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#ifndef _ASM_X86_COCO_H
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#define _ASM_X86_COCO_H
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#include <asm/types.h>
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enum cc_vendor {
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CC_VENDOR_NONE,
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CC_VENDOR_AMD,
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@ -10,5 +12,21 @@ enum cc_vendor {
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};
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void cc_set_vendor(enum cc_vendor v);
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void cc_set_mask(u64 mask);
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#ifdef CONFIG_ARCH_HAS_CC_PLATFORM
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u64 cc_mkenc(u64 val);
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u64 cc_mkdec(u64 val);
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#else
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static inline u64 cc_mkenc(u64 val)
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{
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return val;
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}
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static inline u64 cc_mkdec(u64 val)
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{
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return val;
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}
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#endif
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#endif /* _ASM_X86_COCO_H */
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@ -15,17 +15,12 @@
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cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS))) \
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: (prot))
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/*
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* Macros to add or remove encryption attribute
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*/
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#define pgprot_encrypted(prot) __pgprot(__sme_set(pgprot_val(prot)))
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#define pgprot_decrypted(prot) __pgprot(__sme_clr(pgprot_val(prot)))
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#ifndef __ASSEMBLY__
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#include <linux/spinlock.h>
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#include <asm/x86_init.h>
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#include <asm/pkru.h>
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#include <asm/fpu/api.h>
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#include <asm/coco.h>
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#include <asm-generic/pgtable_uffd.h>
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#include <linux/page_table_check.h>
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@ -38,6 +33,12 @@ void ptdump_walk_pgd_level_debugfs(struct seq_file *m, struct mm_struct *mm,
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void ptdump_walk_pgd_level_checkwx(void);
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void ptdump_walk_user_pgd_level_checkwx(void);
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/*
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* Macros to add or remove encryption attribute
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*/
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#define pgprot_encrypted(prot) __pgprot(cc_mkenc(pgprot_val(prot)))
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#define pgprot_decrypted(prot) __pgprot(cc_mkdec(pgprot_val(prot)))
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#ifdef CONFIG_DEBUG_WX
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#define debug_checkwx() ptdump_walk_pgd_level_checkwx()
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#define debug_checkwx_user() ptdump_walk_user_pgd_level_checkwx()
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@ -604,5 +604,6 @@ out:
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if (sme_me_mask) {
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physical_mask &= ~sme_me_mask;
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cc_set_vendor(CC_VENDOR_AMD);
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cc_set_mask(sme_me_mask);
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}
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}
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@ -1989,6 +1989,7 @@ int set_memory_global(unsigned long addr, int numpages)
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*/
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static int __set_memory_enc_pgtable(unsigned long addr, int numpages, bool enc)
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{
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pgprot_t empty = __pgprot(0);
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struct cpa_data cpa;
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int ret;
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@ -1999,8 +2000,8 @@ static int __set_memory_enc_pgtable(unsigned long addr, int numpages, bool enc)
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memset(&cpa, 0, sizeof(cpa));
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cpa.vaddr = &addr;
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cpa.numpages = numpages;
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cpa.mask_set = enc ? __pgprot(_PAGE_ENC) : __pgprot(0);
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cpa.mask_clr = enc ? __pgprot(0) : __pgprot(_PAGE_ENC);
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cpa.mask_set = enc ? pgprot_encrypted(empty) : pgprot_decrypted(empty);
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cpa.mask_clr = enc ? pgprot_decrypted(empty) : pgprot_encrypted(empty);
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cpa.pgd = init_mm.pgd;
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/* Must avoid aliasing mappings in the highmem code */
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