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Second Round of Renesas ARM Based SoC Updates for v4.19

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* Always enable ARCH_TIMER on SoCs with A7 or A15
 
   All such SoCs have ARCH_TIMER so there is no need for it to be optional.
   This allows clean-up which is included in this change.
 
 * Do not compile r8a7779_platform_cpu_kill when it is unused
 
   This avoids a warning by shuffling code into an existing #ifdef
   r8a7779 is the R-Car H1 SoC
 
 * Add SMP enabler driver for the RZ/N1D (r9a06g032) SoC
 
   This is to allow SMP to be enabled via DT on the r9a06g032
 
 * Stop compiling headsmp-apmu for non-SMP configs
 
   This is a minor clean-up allowing removal of an #ifdef
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Merge tag 'renesas-arm-soc2-for-v4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Second Round of Renesas ARM Based SoC Updates for v4.19

* Always enable ARCH_TIMER on SoCs with A7 or A15

  All such SoCs have ARCH_TIMER so there is no need for it to be optional.
  This allows clean-up which is included in this change.

* Do not compile r8a7779_platform_cpu_kill when it is unused

  This avoids a warning by shuffling code into an existing #ifdef
  r8a7779 is the R-Car H1 SoC

* Add SMP enabler driver for the RZ/N1D (r9a06g032) SoC

  This is to allow SMP to be enabled via DT on the r9a06g032

* Stop compiling headsmp-apmu for non-SMP configs

  This is a minor clean-up allowing removal of an #ifdef

* tag 'renesas-arm-soc2-for-v4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: Always enable ARCH_TIMER on SoCs with A7 and/or A15
  ARM: shmobile: r8a7779: hide unused r8a7779_platform_cpu_kill
  soc: r9a06g032: don't build SMP files for non-SMP config
  ARM: shmobile: Add the R9A06G032 SMP enabler driver
  ARM: shmobile: rcar-gen2: Stop compiling headsmp-apmu on !SMP

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-07-21 14:19:37 -07:00
commit b598b3aaf9
9 changed files with 113 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/mach-shmobile/Kconfig
View File

@ -15,6 +15,7 @@ config ARCH_RCAR_GEN1
config ARCH_RCAR_GEN2
bool
select HAVE_ARM_ARCH_TIMER
select PM
select PM_GENERIC_DOMAINS
select RENESAS_IRQC
@ -58,6 +59,7 @@ config ARCH_R8A73A4
bool "R-Mobile APE6 (R8A73A40)"
select ARCH_RMOBILE
select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER
select RENESAS_IRQC
config ARCH_R8A7740

2
arch/arm/mach-shmobile/Makefile
View File

@ -21,13 +21,13 @@ cpu-y := platsmp.o headsmp.o
# Shared SoC family objects
obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
CFLAGS_setup-rcar-gen2.o += -march=armv7-a
obj-$(CONFIG_ARCH_RCAR_GEN2) += headsmp-apmu.o
obj-$(CONFIG_ARCH_R8A7790) += regulator-quirk-rcar-gen2.o
obj-$(CONFIG_ARCH_R8A7791) += regulator-quirk-rcar-gen2.o
obj-$(CONFIG_ARCH_R8A7793) += regulator-quirk-rcar-gen2.o
# SMP objects
smp-y := $(cpu-y)
smp-$(CONFIG_ARCH_RCAR_GEN2) += headsmp-apmu.o
smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o
smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o
smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o

2
arch/arm/mach-shmobile/headsmp-apmu.S
View File

@ -8,9 +8,7 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
#ifdef CONFIG_SMP
ENTRY(shmobile_boot_apmu)
bl secure_cntvoff_init
b secondary_startup
ENDPROC(shmobile_boot_apmu)
#endif

1
arch/arm/mach-shmobile/setup-r8a73a4.c
View File

@ -18,7 +18,6 @@ static const char *const r8a73a4_boards_compat_dt[] __initconst = {
};
DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
.init_early = shmobile_init_delay,
.init_late = shmobile_init_late,
.dt_compat = r8a73a4_boards_compat_dt,
MACHINE_END

4
arch/arm/mach-shmobile/setup-rcar-gen2.c
View File

@ -59,7 +59,6 @@ static unsigned int __init get_extal_freq(void)
void __init rcar_gen2_timer_init(void)
{
#ifdef CONFIG_ARM_ARCH_TIMER
void __iomem *base;
u32 freq;
@ -101,7 +100,6 @@ void __init rcar_gen2_timer_init(void)
}
iounmap(base);
#endif /* CONFIG_ARM_ARCH_TIMER */
of_clk_init(NULL);
timer_probe();
@ -187,7 +185,6 @@ static const char * const rcar_gen2_boards_compat_dt[] __initconst = {
};
DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)")
.init_early = shmobile_init_delay,
.init_late = shmobile_init_late,
.init_time = rcar_gen2_timer_init,
.reserve = rcar_gen2_reserve,
@ -202,7 +199,6 @@ static const char * const rz_g1_boards_compat_dt[] __initconst = {
};
DT_MACHINE_START(RZ_G1_DT, "Generic RZ/G1 (Flattened Device Tree)")
.init_early = shmobile_init_delay,
.init_late = shmobile_init_late,
.init_time = rcar_gen2_timer_init,
.reserve = rcar_gen2_reserve,

22
arch/arm/mach-shmobile/smp-r8a7779.c
View File

@ -23,17 +23,6 @@
#define AVECR IOMEM(0xfe700040)
#define R8A7779_SCU_BASE 0xf0000000
static int r8a7779_platform_cpu_kill(unsigned int cpu)
{
int ret = -EIO;
cpu = cpu_logical_map(cpu);
if (cpu)
ret = rcar_sysc_power_down_cpu(cpu);
return ret ? ret : 1;
}
static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
int ret = -EIO;
@ -55,6 +44,17 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
}
#ifdef CONFIG_HOTPLUG_CPU
static int r8a7779_platform_cpu_kill(unsigned int cpu)
{
int ret = -EIO;
cpu = cpu_logical_map(cpu);
if (cpu)
ret = rcar_sysc_power_down_cpu(cpu);
return ret ? ret : 1;
}
static int r8a7779_cpu_kill(unsigned int cpu)
{
if (shmobile_smp_scu_cpu_kill(cpu))

8
arch/arm/mach-shmobile/timer.c
View File

@ -32,14 +32,6 @@ void __init shmobile_init_delay(void)
for_each_child_of_node(cpus, np) {
u32 freq;
if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER) &&
(of_device_is_compatible(np, "arm,cortex-a7") ||
of_device_is_compatible(np, "arm,cortex-a15"))) {
of_node_put(np);
of_node_put(cpus);
return;
}
if (!of_property_read_u32(np, "clock-frequency", &freq))
max_freq = max(max_freq, freq);
}

3
drivers/soc/renesas/Makefile
View File

@ -18,6 +18,9 @@ obj-$(CONFIG_SYSC_R8A77970) += r8a77970-sysc.o
obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o
obj-$(CONFIG_SYSC_R8A77990) += r8a77990-sysc.o
obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o
ifdef CONFIG_SMP
obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o
endif
# Family
obj-$(CONFIG_RST_RCAR) += rcar-rst.o

96
drivers/soc/renesas/r9a06g032-smp.c Normal file
View File

@ -0,0 +1,96 @@
// SPDX-License-Identifier: GPL-2.0
/*
* R9A06G032 Second CA7 enabler.
*
* Copyright (C) 2018 Renesas Electronics Europe Limited
*
* Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
* Derived from actions,s500-smp
*/
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/smp.h>
/*
* The second CPU is parked in ROM at boot time. It requires waking it after
* writing an address into the BOOTADDR register of sysctrl.
*
* So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
*
* *However* the BOOTADDR register is not available when the kernel
* starts in NONSEC mode.
*
* So for NONSEC mode, the bootloader re-parks the second CPU into a pen
* in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
* which is not restricted.
*/
static void __iomem *cpu_bootaddr;
static DEFINE_SPINLOCK(cpu_lock);
static int
r9a06g032_smp_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
if (!cpu_bootaddr)
return -ENODEV;
spin_lock(&cpu_lock);
writel(__pa_symbol(secondary_startup), cpu_bootaddr);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
spin_unlock(&cpu_lock);
return 0;
}
static void __init r9a06g032_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *dn;
int ret = -EINVAL, dns;
u32 bootaddr;
dn = of_get_cpu_node(1, NULL);
if (!dn) {
pr_err("CPU#1: missing device tree node\n");
return;
}
/*
* Determine the address from which the CPU is polling.
* The bootloader *does* change this property.
* Note: The property can be either 64 or 32 bits, so handle both cases
*/
if (of_find_property(dn, "cpu-release-addr", &dns)) {
if (dns == sizeof(u64)) {
u64 temp;
ret = of_property_read_u64(dn,
"cpu-release-addr", &temp);
bootaddr = temp;
} else {
ret = of_property_read_u32(dn,
"cpu-release-addr",
&bootaddr);
}
}
of_node_put(dn);
if (ret) {
pr_err("CPU#1: invalid cpu-release-addr property\n");
return;
}
pr_info("CPU#1: cpu-release-addr %08x\n", bootaddr);
cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr));
}
static const struct smp_operations r9a06g032_smp_ops __initconst = {
.smp_prepare_cpus = r9a06g032_smp_prepare_cpus,
.smp_boot_secondary = r9a06g032_smp_boot_secondary,
};
CPU_METHOD_OF_DECLARE(r9a06g032_smp,
"renesas,r9a06g032-smp", &r9a06g032_smp_ops);