drm/amdgpu: correct smu v13.0.6 umc ras error check
correct smu v13.0.0 umc ras error check Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -88,7 +88,7 @@ static void umc_v12_0_reset_error_count(struct amdgpu_device *adev)
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umc_v12_0_reset_error_count_per_channel, NULL);
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}
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static bool umc_v12_0_is_uncorrectable_error(uint64_t mc_umc_status)
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bool umc_v12_0_is_uncorrectable_error(uint64_t mc_umc_status)
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{
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return ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
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(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
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@ -96,7 +96,7 @@ static bool umc_v12_0_is_uncorrectable_error(uint64_t mc_umc_status)
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1));
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}
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static bool umc_v12_0_is_correctable_error(uint64_t mc_umc_status)
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bool umc_v12_0_is_correctable_error(uint64_t mc_umc_status)
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{
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return (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1 ||
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@ -117,6 +117,9 @@
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(pa) |= (UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) << UMC_V12_0_PA_CH6_BIT); \
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} while (0)
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bool umc_v12_0_is_uncorrectable_error(uint64_t mc_umc_status);
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bool umc_v12_0_is_correctable_error(uint64_t mc_umc_status);
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extern const uint32_t
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umc_v12_0_channel_idx_tbl[]
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[UMC_V12_0_UMC_INSTANCE_NUM]
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@ -48,6 +48,7 @@
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#include "smu_cmn.h"
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#include "mp/mp_13_0_6_offset.h"
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#include "mp/mp_13_0_6_sh_mask.h"
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#include "umc_v12_0.h"
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#undef MP1_Public
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#undef smnMP1_FIRMWARE_FLAGS
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@ -2481,7 +2482,7 @@ static int mca_decode_mca_ipid(struct amdgpu_device *adev, enum amdgpu_mca_error
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return 0;
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}
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static int mca_normal_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
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static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
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enum amdgpu_mca_error_type type, int idx, uint32_t *count)
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{
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uint64_t status0;
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@ -2491,10 +2492,15 @@ static int mca_normal_mca_get_err_count(const struct mca_ras_info *mca_ras, stru
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if (ret)
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return ret;
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if (REG_GET_FIELD(status0, MCMP1_STATUST0, Val))
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*count = 1;
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else
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if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
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*count = 0;
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return 0;
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}
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if (type == AMDGPU_MCA_ERROR_TYPE_UE && umc_v12_0_is_uncorrectable_error(status0))
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*count = 1;
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else if (type == AMDGPU_MCA_ERROR_TYPE_CE && umc_v12_0_is_correctable_error(status0))
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*count = 1;
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return 0;
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}
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@ -2608,7 +2614,7 @@ static const struct mca_ras_info mca_ras_table[] = {
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{
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.blkid = AMDGPU_RAS_BLOCK__UMC,
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.ip = AMDGPU_MCA_IP_UMC,
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.get_err_count = mca_normal_mca_get_err_count,
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.get_err_count = mca_umc_mca_get_err_count,
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}, {
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.blkid = AMDGPU_RAS_BLOCK__GFX,
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.ip = AMDGPU_MCA_IP_MP5,
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