drm/amdgpu: Use new mode2 reset interface for RV.
Integrate the mode2 reset into rest sequence. v2: Check ppfuncs pointer for NULL Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3525,6 +3525,7 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
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case CHIP_VEGA20:
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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case CHIP_RAVEN:
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break;
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default:
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goto disabled;
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@ -509,6 +509,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
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return 0;
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}
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static int soc15_mode2_reset(struct amdgpu_device *adev)
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{
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if (!adev->powerplay.pp_funcs ||
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!adev->powerplay.pp_funcs->asic_reset_mode_2)
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return -ENOENT;
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return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle);
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}
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static enum amd_reset_method
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soc15_asic_reset_method(struct amdgpu_device *adev)
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{
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@ -547,14 +556,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
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static int soc15_asic_reset(struct amdgpu_device *adev)
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{
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int ret;
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if (soc15_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
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ret = soc15_asic_baco_reset(adev);
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else
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ret = soc15_asic_mode1_reset(adev);
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return ret;
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switch (soc15_asic_reset_method(adev)) {
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case AMD_RESET_METHOD_BACO:
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return soc15_asic_baco_reset(adev);
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case AMD_RESET_METHOD_MODE2:
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return soc15_mode2_reset(adev);
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default:
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return soc15_asic_mode1_reset(adev);
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}
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}
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/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
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