drm/amdgpu: implement hdp v4_0 ras functions
implement hdp v4_0 ras functions, including ras init/fini, query/reset_error_counter Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -59,12 +59,31 @@ static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
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HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
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}
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static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
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err_data->ue_count = 0;
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err_data->ce_count = 0;
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if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
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return;
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/* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
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err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
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};
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static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
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{
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if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
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return;
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/*read back hdp ras counter to reset it to 0 */
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RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
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if (adev->asic_type >= CHIP_ALDEBARAN)
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WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
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else
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/*read back hdp ras counter to reset it to 0 */
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RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
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}
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static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
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@ -130,6 +149,13 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
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WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
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}
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const struct amdgpu_hdp_ras_funcs hdp_v4_0_ras_funcs = {
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.ras_late_init = amdgpu_hdp_ras_late_init,
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.ras_fini = amdgpu_hdp_ras_fini,
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.query_ras_error_count = hdp_v4_0_query_ras_error_count,
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.reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
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};
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const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
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.flush_hdp = hdp_v4_0_flush_hdp,
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.invalidate_hdp = hdp_v4_0_invalidate_hdp,
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@ -27,5 +27,6 @@
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#include "soc15_common.h"
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extern const struct amdgpu_hdp_funcs hdp_v4_0_funcs;
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extern const struct amdgpu_hdp_ras_funcs hdp_v4_0_ras_funcs;
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#endif
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