drm/amd/display: Add DCN3.1 DIO
Add support for the DIO (Display IO) block of DCN3.1 which controls
legacy HDMI/DP stream/link encoding.
HW Blocks:
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Includes some updates to core logic for link encoder assignment and
future support for new high bandwidth output.
v2: squash in unused variable fix (Alex)
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas
Alex Deucher
parent
d8a2b4f3a9
commit
cbaf919f33
@ -2875,8 +2875,16 @@ bool dc_link_setup_psr(struct dc_link *link,
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psr_context->psr_level.u32all = 0;
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/*skip power down the single pipe since it blocks the cstate*/
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
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psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
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if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10)
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psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
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}
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#else
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if (link->ctx->asic_id.chip_family >= FAMILY_RV)
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psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
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#endif
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/* SMU will perform additional powerdown sequence.
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* For unsupported ASICs, set psr_level flag to skip PSR
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@ -3208,8 +3216,14 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
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dp_get_panel_mode(pipe_ctx->stream->link);
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config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
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/*stream_enc_inst*/
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config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
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config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
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config.link_enc_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
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config.phy_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
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#endif
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config.dpms_off = dpms_off;
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config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
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config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
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@ -2121,6 +2121,16 @@ enum dc_status dc_validate_global_state(
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if (!new_ctx)
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return DC_ERROR_UNEXPECTED;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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/*
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* Update link encoder to stream assignment.
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* TODO: Split out reason allocation from validation.
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*/
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if (dc->res_pool->funcs->link_encs_assign)
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dc->res_pool->funcs->link_encs_assign(
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dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
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#endif
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if (dc->res_pool->funcs->validate_global) {
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result = dc->res_pool->funcs->validate_global(dc, new_ctx);
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@ -160,6 +160,14 @@ struct dcn10_link_enc_registers {
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uint32_t PHYA_LINK_CNTL2;
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uint32_t PHYB_LINK_CNTL2;
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uint32_t PHYC_LINK_CNTL2;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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uint32_t DIO_LINKA_CNTL;
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uint32_t DIO_LINKB_CNTL;
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uint32_t DIO_LINKC_CNTL;
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uint32_t DIO_LINKD_CNTL;
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uint32_t DIO_LINKE_CNTL;
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uint32_t DIO_LINKF_CNTL;
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#endif
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};
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#define LE_SF(reg_name, field_name, post_fix)\
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@ -459,17 +467,29 @@ struct dcn10_link_enc_registers {
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type DPCS_TX_DATA_SWAP_10_BIT;\
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type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\
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type RDPCS_TX_CLK_EN
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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#define DCN31_LINK_ENCODER_REG_FIELD_LIST(type) \
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type ENC_TYPE_SEL;\
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type HPO_DP_ENC_SEL;\
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type HPO_HDMI_ENC_SEL
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#endif
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struct dcn10_link_enc_shift {
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DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
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DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
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DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
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#endif
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};
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struct dcn10_link_enc_mask {
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DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
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DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
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DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
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#endif
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};
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struct dcn10_link_encoder {
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406
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
Normal file
406
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
Normal file
@ -0,0 +1,406 @@
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include "core_types.h"
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#include "link_encoder.h"
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#include "dcn31_dio_link_encoder.h"
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#include "stream_encoder.h"
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#include "i2caux_interface.h"
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#include "dc_bios_types.h"
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#include "gpio_service_interface.h"
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#include "link_enc_cfg.h"
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#include "dc_dmub_srv.h"
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#define CTX \
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enc10->base.ctx
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#define DC_LOGGER \
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enc10->base.ctx->logger
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#define REG(reg)\
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(enc10->link_regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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enc10->link_shift->field_name, enc10->link_mask->field_name
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#define IND_REG(index) \
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(enc10->link_regs->index)
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#define AUX_REG(reg)\
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(enc10->aux_regs->reg)
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#define AUX_REG_READ(reg_name) \
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dm_read_reg(CTX, AUX_REG(reg_name))
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#define AUX_REG_WRITE(reg_name, val) \
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dm_write_reg(CTX, AUX_REG(reg_name), val)
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void dcn31_link_encoder_set_dio_phy_mux(
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struct link_encoder *enc,
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enum encoder_type_select sel,
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uint32_t hpo_inst)
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{
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struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
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switch (enc->transmitter) {
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case TRANSMITTER_UNIPHY_A:
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if (sel == ENCODER_TYPE_HDMI_FRL)
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REG_UPDATE(DIO_LINKA_CNTL,
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HPO_HDMI_ENC_SEL, hpo_inst);
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else if (sel == ENCODER_TYPE_DP_128B132B)
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REG_UPDATE(DIO_LINKA_CNTL,
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HPO_DP_ENC_SEL, hpo_inst);
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REG_UPDATE(DIO_LINKA_CNTL,
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ENC_TYPE_SEL, sel);
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break;
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case TRANSMITTER_UNIPHY_B:
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if (sel == ENCODER_TYPE_HDMI_FRL)
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REG_UPDATE(DIO_LINKB_CNTL,
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HPO_HDMI_ENC_SEL, hpo_inst);
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else if (sel == ENCODER_TYPE_DP_128B132B)
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REG_UPDATE(DIO_LINKB_CNTL,
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HPO_DP_ENC_SEL, hpo_inst);
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REG_UPDATE(DIO_LINKB_CNTL,
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ENC_TYPE_SEL, sel);
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break;
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case TRANSMITTER_UNIPHY_C:
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if (sel == ENCODER_TYPE_HDMI_FRL)
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REG_UPDATE(DIO_LINKC_CNTL,
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HPO_HDMI_ENC_SEL, hpo_inst);
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else if (sel == ENCODER_TYPE_DP_128B132B)
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REG_UPDATE(DIO_LINKC_CNTL,
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HPO_DP_ENC_SEL, hpo_inst);
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REG_UPDATE(DIO_LINKC_CNTL,
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ENC_TYPE_SEL, sel);
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break;
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case TRANSMITTER_UNIPHY_D:
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if (sel == ENCODER_TYPE_HDMI_FRL)
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REG_UPDATE(DIO_LINKD_CNTL,
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HPO_HDMI_ENC_SEL, hpo_inst);
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else if (sel == ENCODER_TYPE_DP_128B132B)
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REG_UPDATE(DIO_LINKD_CNTL,
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HPO_DP_ENC_SEL, hpo_inst);
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REG_UPDATE(DIO_LINKD_CNTL,
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ENC_TYPE_SEL, sel);
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break;
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case TRANSMITTER_UNIPHY_E:
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if (sel == ENCODER_TYPE_HDMI_FRL)
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REG_UPDATE(DIO_LINKE_CNTL,
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HPO_HDMI_ENC_SEL, hpo_inst);
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else if (sel == ENCODER_TYPE_DP_128B132B)
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REG_UPDATE(DIO_LINKE_CNTL,
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HPO_DP_ENC_SEL, hpo_inst);
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REG_UPDATE(DIO_LINKE_CNTL,
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ENC_TYPE_SEL, sel);
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break;
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case TRANSMITTER_UNIPHY_F:
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if (sel == ENCODER_TYPE_HDMI_FRL)
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REG_UPDATE(DIO_LINKF_CNTL,
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HPO_HDMI_ENC_SEL, hpo_inst);
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else if (sel == ENCODER_TYPE_DP_128B132B)
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REG_UPDATE(DIO_LINKF_CNTL,
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HPO_DP_ENC_SEL, hpo_inst);
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REG_UPDATE(DIO_LINKF_CNTL,
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ENC_TYPE_SEL, sel);
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break;
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default:
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/* Do nothing */
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break;
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}
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}
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void enc31_hw_init(struct link_encoder *enc)
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{
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struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
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/*
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00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
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01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
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02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
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03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
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04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
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05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
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06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
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07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
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*/
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/*
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AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
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AUX_RX_START_WINDOW = 1 [6:4]
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AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
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AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1
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AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
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AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0
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AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1
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AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1
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AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3
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AUX_RX_DETECTION_THRESHOLD [30:28] = 1
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*/
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AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
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AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
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//AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
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// Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
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// 27MHz -> 0xd
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// 100MHz -> 0x32
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// 48MHz -> 0x18
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#ifdef CLEANUP_FIXME
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/*from display_init*/
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REG_WRITE(RDPCSTX_DEBUG_CONFIG, 0);
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#endif
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// Set TMDS_CTL0 to 1. This is a legacy setting.
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REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
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/*HW default is 5*/
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REG_UPDATE(RDPCSTX_CNTL,
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RDPCS_TX_FIFO_RD_START_DELAY, 4);
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dcn10_aux_initialize(enc10);
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}
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static const struct link_encoder_funcs dcn31_link_enc_funcs = {
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.read_state = link_enc2_read_state,
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.validate_output_with_stream =
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dcn30_link_encoder_validate_output_with_stream,
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.hw_init = enc31_hw_init,
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.setup = dcn10_link_encoder_setup,
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.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
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.enable_dp_output = dcn31_link_encoder_enable_dp_output,
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.enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output,
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.disable_output = dcn31_link_encoder_disable_output,
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.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
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.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
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.update_mst_stream_allocation_table =
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dcn10_link_encoder_update_mst_stream_allocation_table,
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.psr_program_dp_dphy_fast_training =
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dcn10_psr_program_dp_dphy_fast_training,
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.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
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.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
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.enable_hpd = dcn10_link_encoder_enable_hpd,
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.disable_hpd = dcn10_link_encoder_disable_hpd,
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.is_dig_enabled = dcn10_is_dig_enabled,
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.destroy = dcn10_link_encoder_destroy,
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.fec_set_enable = enc2_fec_set_enable,
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.fec_set_ready = enc2_fec_set_ready,
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.fec_is_active = enc2_fec_is_active,
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.get_dig_frontend = dcn10_get_dig_frontend,
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.get_dig_mode = dcn10_get_dig_mode,
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.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
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.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
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.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
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};
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void dcn31_link_encoder_construct(
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struct dcn20_link_encoder *enc20,
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const struct encoder_init_data *init_data,
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const struct encoder_feature_support *enc_features,
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const struct dcn10_link_enc_registers *link_regs,
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const struct dcn10_link_enc_aux_registers *aux_regs,
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const struct dcn10_link_enc_hpd_registers *hpd_regs,
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const struct dcn10_link_enc_shift *link_shift,
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const struct dcn10_link_enc_mask *link_mask)
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{
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struct bp_encoder_cap_info bp_cap_info = {0};
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const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
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enum bp_result result = BP_RESULT_OK;
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struct dcn10_link_encoder *enc10 = &enc20->enc10;
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enc10->base.funcs = &dcn31_link_enc_funcs;
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enc10->base.ctx = init_data->ctx;
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enc10->base.id = init_data->encoder;
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enc10->base.hpd_source = init_data->hpd_source;
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enc10->base.connector = init_data->connector;
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enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
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enc10->base.features = *enc_features;
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enc10->base.transmitter = init_data->transmitter;
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/* set the flag to indicate whether driver poll the I2C data pin
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* while doing the DP sink detect
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*/
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/* if (dal_adapter_service_is_feature_supported(as,
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FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
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enc10->base.features.flags.bits.
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DP_SINK_DETECT_POLL_DATA_PIN = true;*/
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enc10->base.output_signals =
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SIGNAL_TYPE_DVI_SINGLE_LINK |
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SIGNAL_TYPE_DVI_DUAL_LINK |
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SIGNAL_TYPE_LVDS |
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SIGNAL_TYPE_DISPLAY_PORT |
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SIGNAL_TYPE_DISPLAY_PORT_MST |
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SIGNAL_TYPE_EDP |
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SIGNAL_TYPE_HDMI_TYPE_A;
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/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
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* SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
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* SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
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* DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
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* Prefer DIG assignment is decided by board design.
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* For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
|
||||
* and VBIOS will filter out 7 UNIPHY for DCE 8.0.
|
||||
* By this, adding DIGG should not hurt DCE 8.0.
|
||||
* This will let DCE 8.1 share DCE 8.0 as much as possible
|
||||
*/
|
||||
|
||||
enc10->link_regs = link_regs;
|
||||
enc10->aux_regs = aux_regs;
|
||||
enc10->hpd_regs = hpd_regs;
|
||||
enc10->link_shift = link_shift;
|
||||
enc10->link_mask = link_mask;
|
||||
|
||||
switch (enc10->base.transmitter) {
|
||||
case TRANSMITTER_UNIPHY_A:
|
||||
enc10->base.preferred_engine = ENGINE_ID_DIGA;
|
||||
break;
|
||||
case TRANSMITTER_UNIPHY_B:
|
||||
enc10->base.preferred_engine = ENGINE_ID_DIGB;
|
||||
break;
|
||||
case TRANSMITTER_UNIPHY_C:
|
||||
enc10->base.preferred_engine = ENGINE_ID_DIGC;
|
||||
break;
|
||||
case TRANSMITTER_UNIPHY_D:
|
||||
enc10->base.preferred_engine = ENGINE_ID_DIGD;
|
||||
break;
|
||||
case TRANSMITTER_UNIPHY_E:
|
||||
enc10->base.preferred_engine = ENGINE_ID_DIGE;
|
||||
break;
|
||||
case TRANSMITTER_UNIPHY_F:
|
||||
enc10->base.preferred_engine = ENGINE_ID_DIGF;
|
||||
break;
|
||||
default:
|
||||
ASSERT_CRITICAL(false);
|
||||
enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
|
||||
}
|
||||
|
||||
/* default to one to mirror Windows behavior */
|
||||
enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
|
||||
|
||||
result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
|
||||
enc10->base.id, &bp_cap_info);
|
||||
|
||||
/* Override features with DCE-specific values */
|
||||
if (result == BP_RESULT_OK) {
|
||||
enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
|
||||
bp_cap_info.DP_HBR2_EN;
|
||||
enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
|
||||
bp_cap_info.DP_HBR3_EN;
|
||||
enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
|
||||
enc10->base.features.flags.bits.DP_IS_USB_C =
|
||||
bp_cap_info.DP_IS_USB_C;
|
||||
} else {
|
||||
DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
|
||||
__func__,
|
||||
result);
|
||||
}
|
||||
if (enc10->base.ctx->dc->debug.hdmi20_disable) {
|
||||
enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void dcn31_link_encoder_construct_minimal(
|
||||
struct dcn20_link_encoder *enc20,
|
||||
struct dc_context *ctx,
|
||||
const struct encoder_feature_support *enc_features,
|
||||
const struct dcn10_link_enc_registers *link_regs,
|
||||
enum engine_id eng_id)
|
||||
{
|
||||
struct dcn10_link_encoder *enc10 = &enc20->enc10;
|
||||
|
||||
enc10->base.funcs = &dcn31_link_enc_funcs;
|
||||
enc10->base.ctx = ctx;
|
||||
enc10->base.id.type = OBJECT_TYPE_ENCODER;
|
||||
enc10->base.hpd_source = HPD_SOURCEID_UNKNOWN;
|
||||
enc10->base.connector.type = OBJECT_TYPE_CONNECTOR;
|
||||
enc10->base.preferred_engine = eng_id;
|
||||
enc10->base.features = *enc_features;
|
||||
enc10->base.transmitter = TRANSMITTER_UNKNOWN;
|
||||
enc10->link_regs = link_regs;
|
||||
|
||||
enc10->base.output_signals =
|
||||
SIGNAL_TYPE_DISPLAY_PORT |
|
||||
SIGNAL_TYPE_DISPLAY_PORT_MST |
|
||||
SIGNAL_TYPE_EDP;
|
||||
}
|
||||
|
||||
void dcn31_link_encoder_enable_dp_output(
|
||||
struct link_encoder *enc,
|
||||
const struct dc_link_settings *link_settings,
|
||||
enum clock_source_id clock_source)
|
||||
{
|
||||
/* Enable transmitter and encoder. */
|
||||
if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
|
||||
|
||||
dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source);
|
||||
|
||||
} else {
|
||||
|
||||
/** @todo Handle transmitter with programmable mapping to link encoder. */
|
||||
}
|
||||
}
|
||||
|
||||
void dcn31_link_encoder_enable_dp_mst_output(
|
||||
struct link_encoder *enc,
|
||||
const struct dc_link_settings *link_settings,
|
||||
enum clock_source_id clock_source)
|
||||
{
|
||||
/* Enable transmitter and encoder. */
|
||||
if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
|
||||
|
||||
dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
|
||||
|
||||
} else {
|
||||
|
||||
/** @todo Handle transmitter with programmable mapping to link encoder. */
|
||||
}
|
||||
}
|
||||
|
||||
void dcn31_link_encoder_disable_output(
|
||||
struct link_encoder *enc,
|
||||
enum signal_type signal)
|
||||
{
|
||||
/* Disable transmitter and encoder. */
|
||||
if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
|
||||
|
||||
dcn10_link_encoder_disable_output(enc, signal);
|
||||
|
||||
} else {
|
||||
|
||||
/** @todo Handle transmitter with programmable mapping to link encoder. */
|
||||
}
|
||||
}
|
||||
|
||||
246
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
Normal file
246
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
Normal file
@ -0,0 +1,246 @@
|
||||
/*
|
||||
* Copyright 2012-15 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DC_LINK_ENCODER__DCN31_H__
|
||||
#define __DC_LINK_ENCODER__DCN31_H__
|
||||
|
||||
#include "dcn30/dcn30_dio_link_encoder.h"
|
||||
|
||||
|
||||
#define LE_DCN31_REG_LIST(id)\
|
||||
LE_DCN3_REG_LIST(id),\
|
||||
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
|
||||
SR(DIO_LINKA_CNTL), \
|
||||
SR(DIO_LINKB_CNTL), \
|
||||
SR(DIO_LINKC_CNTL), \
|
||||
SR(DIO_LINKD_CNTL), \
|
||||
SR(DIO_LINKE_CNTL), \
|
||||
SR(DIO_LINKF_CNTL)
|
||||
|
||||
#define LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh) \
|
||||
LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
|
||||
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
|
||||
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
|
||||
LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
|
||||
LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
|
||||
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\
|
||||
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\
|
||||
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\
|
||||
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\
|
||||
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\
|
||||
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\
|
||||
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\
|
||||
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \
|
||||
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\
|
||||
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\
|
||||
LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\
|
||||
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\
|
||||
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
|
||||
LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\
|
||||
LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\
|
||||
LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\
|
||||
LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh)
|
||||
|
||||
#define DPCS_DCN31_REG_LIST(id) \
|
||||
SRI(TMDS_CTL_BITS, DIG, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_CNTL, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \
|
||||
SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \
|
||||
SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \
|
||||
SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
|
||||
SR(RDPCSTX0_RDPCSTX_SCRATCH), \
|
||||
SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\
|
||||
SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)
|
||||
|
||||
#define DPCS_DCN31_MASK_SH_LIST(mask_sh)\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\
|
||||
LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh)
|
||||
|
||||
void dcn31_link_encoder_construct(
|
||||
struct dcn20_link_encoder *enc20,
|
||||
const struct encoder_init_data *init_data,
|
||||
const struct encoder_feature_support *enc_features,
|
||||
const struct dcn10_link_enc_registers *link_regs,
|
||||
const struct dcn10_link_enc_aux_registers *aux_regs,
|
||||
const struct dcn10_link_enc_hpd_registers *hpd_regs,
|
||||
const struct dcn10_link_enc_shift *link_shift,
|
||||
const struct dcn10_link_enc_mask *link_mask);
|
||||
|
||||
/*
|
||||
* Create a minimal link encoder object with no dc_link object associated with it.
|
||||
*/
|
||||
void dcn31_link_encoder_construct_minimal(
|
||||
struct dcn20_link_encoder *enc20,
|
||||
struct dc_context *ctx,
|
||||
const struct encoder_feature_support *enc_features,
|
||||
const struct dcn10_link_enc_registers *link_regs,
|
||||
enum engine_id eng_id);
|
||||
|
||||
void dcn31_link_encoder_set_dio_phy_mux(
|
||||
struct link_encoder *enc,
|
||||
enum encoder_type_select sel,
|
||||
uint32_t hpo_inst);
|
||||
|
||||
/*
|
||||
* Enable DP transmitter and its encoder.
|
||||
*/
|
||||
void dcn31_link_encoder_enable_dp_output(
|
||||
struct link_encoder *enc,
|
||||
const struct dc_link_settings *link_settings,
|
||||
enum clock_source_id clock_source);
|
||||
|
||||
/*
|
||||
* Enable DP transmitter and its encoder in MST mode.
|
||||
*/
|
||||
void dcn31_link_encoder_enable_dp_mst_output(
|
||||
struct link_encoder *enc,
|
||||
const struct dc_link_settings *link_settings,
|
||||
enum clock_source_id clock_source);
|
||||
|
||||
/*
|
||||
* Disable transmitter and its encoder.
|
||||
*/
|
||||
void dcn31_link_encoder_disable_output(
|
||||
struct link_encoder *enc,
|
||||
enum signal_type signal);
|
||||
|
||||
#endif /* __DC_LINK_ENCODER__DCN31_H__ */
|
||||
@ -127,6 +127,14 @@ struct link_enc_state {
|
||||
|
||||
};
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
|
||||
enum encoder_type_select {
|
||||
ENCODER_TYPE_DIG = 0,
|
||||
ENCODER_TYPE_HDMI_FRL = 1,
|
||||
ENCODER_TYPE_DP_128B132B = 2
|
||||
};
|
||||
#endif
|
||||
|
||||
struct link_encoder_funcs {
|
||||
void (*read_state)(
|
||||
struct link_encoder *enc, struct link_enc_state *s);
|
||||
@ -185,6 +193,12 @@ struct link_encoder_funcs {
|
||||
|
||||
enum signal_type (*get_dig_mode)(
|
||||
struct link_encoder *enc);
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
|
||||
void (*set_dio_phy_mux)(
|
||||
struct link_encoder *enc,
|
||||
enum encoder_type_select sel,
|
||||
uint32_t hpo_inst);
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user