drm/amd/display: Add read backlight interface
[Why & How] Add read backlight interface to get ABM data. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher
parent
6ee90e88b9
commit
ccc875052f
@ -708,3 +708,4 @@ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
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"\tlink: %d\n",
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stream->link->link_index);
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}
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@ -46,6 +46,8 @@
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SR(BL1_PWM_USER_LEVEL), \
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SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
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SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
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SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
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SR(DC_ABM1_ACE_THRES_12), \
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SR(BIOS_SCRATCH_2)
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#define ABM_DCN10_REG_LIST(id)\
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@ -60,6 +62,8 @@
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SRI(BL1_PWM_USER_LEVEL, ABM, id), \
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SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
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SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
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SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
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SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
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NBIO_SR(BIOS_SCRATCH_2)
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#define ABM_DCN20_REG_LIST() \
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@ -74,10 +78,12 @@
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SR(BL1_PWM_USER_LEVEL), \
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SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
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SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
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SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
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SR(DC_ABM1_ACE_THRES_12), \
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NBIO_SR(BIOS_SCRATCH_2)
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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#define ABM_DCN301_REG_LIST(id)\
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#define ABM_DCN30_REG_LIST(id)\
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ABM_COMMON_REG_LIST_DCE_BASE(), \
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SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
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SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
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@ -89,6 +95,8 @@
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SRI(BL1_PWM_USER_LEVEL, ABM, id), \
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SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
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SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
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SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
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SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
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NBIO_SR(BIOS_SCRATCH_2)
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#endif
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@ -208,6 +216,8 @@ struct dce_abm_registers {
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uint32_t BL1_PWM_USER_LEVEL;
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uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
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uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
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uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;
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uint32_t DC_ABM1_ACE_THRES_12;
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uint32_t MASTER_COMM_CNTL_REG;
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uint32_t MASTER_COMM_CMD_REG;
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uint32_t MASTER_COMM_DATA_REG1;
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@ -46,13 +46,14 @@
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#define FN(reg_name, field_name) \
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dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_name
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static unsigned int calculate_16_bit_backlight_from_pwm(struct dce_panel_cntl *dce_panel_cntl)
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static unsigned int dce_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)
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{
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uint64_t current_backlight;
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uint32_t round_result;
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uint32_t pwm_period_cntl, bl_period, bl_int_count;
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uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
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uint32_t bl_period_mask, bl_pwm_mask;
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struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
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pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
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REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
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@ -150,7 +151,7 @@ static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
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REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
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BL_PWM_GRP1_REG_LOCK, 0);
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current_backlight = calculate_16_bit_backlight_from_pwm(dce_panel_cntl);
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current_backlight = dce_get_16_bit_backlight_from_pwm(panel_cntl);
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return current_backlight;
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}
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@ -273,6 +274,7 @@ static const struct panel_cntl_funcs dce_link_panel_cntl_funcs = {
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.is_panel_powered_on = dce_is_panel_powered_on,
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.store_backlight_level = dce_store_backlight_level,
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.driver_set_backlight = dce_driver_set_backlight,
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.get_current_backlight = dce_get_16_bit_backlight_from_pwm,
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};
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void dce_panel_cntl_construct(
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@ -340,7 +340,7 @@ static const struct dce110_clk_src_mask cs_mask = {
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#define abm_regs(id)\
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[id] = {\
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ABM_DCN301_REG_LIST(id)\
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ABM_DCN30_REG_LIST(id)\
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}
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static const struct dce_abm_registers abm_regs[] = {
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@ -49,6 +49,7 @@ struct panel_cntl_funcs {
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void (*store_backlight_level)(struct panel_cntl *panel_cntl);
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void (*driver_set_backlight)(struct panel_cntl *panel_cntl,
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uint32_t backlight_pwm_u16_16);
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uint32_t (*get_current_backlight)(struct panel_cntl *panel_cntl);
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};
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struct panel_cntl_init_data {
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