x86: clean up cpu capabilities in arch/x86/kernel/cpu/intel.c
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -143,12 +143,12 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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unsigned eax = cpuid_eax(10);
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/* Check for version and the number of counters */
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if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
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set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
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}
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/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
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if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
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clear_bit(X86_FEATURE_SEP, c->x86_capability);
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clear_cpu_cap(c, X86_FEATURE_SEP);
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/*
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* Names for the Pentium II/Celeron processors
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@ -209,19 +209,19 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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#endif
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if (cpu_has_xmm2)
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set_bit(X86_FEATURE_LFENCE_RDTSC, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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if (c->x86 == 15) {
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set_bit(X86_FEATURE_P4, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_P4);
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}
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if (c->x86 == 6)
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set_bit(X86_FEATURE_P3, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_P3);
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if (cpu_has_ds) {
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unsigned int l1;
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rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
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if (!(l1 & (1<<11)))
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set_bit(X86_FEATURE_BTS, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_BTS);
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if (!(l1 & (1<<12)))
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set_bit(X86_FEATURE_PEBS, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_PEBS);
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}
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if (cpu_has_bts)
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