drm/amd/display: Add DP 2.0 DCCG
HW Blocks:
+--------+ +-----+ +------+
| OPTC | | HDA | | HUBP |
+--------+ +-----+ +------+
| | |
| | |
HPO ====|==========|========|====
| | v |
| | +-----+ |
| | | APG | |
| | +-----+ |
| | | |
| v v v
| +---------------------+
| | HPO Stream Encoder |
| +---------------------+
| |
| v
| +--------------------+
| | HPO Link Encoder |
| +--------------------+
| |
v ===============|=============
v
+------------------+
| DIO Output Mux |
+------------------+
|
v
+-----+
| PHY |
+-----+
| PHYD32CLK[0]
v
+------+
| DCCG |
+------+
|
v
SYMCLK32
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Fangzhi Zuo
Alex Deucher
parent
3bc8d92146
commit
d76b12da98
@ -42,6 +42,155 @@
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#define DC_LOGGER \
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dccg->ctx->logger
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void dccg31_set_dpstreamclk(
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struct dccg *dccg,
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enum hdmistreamclk_source src,
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int otg_inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* enabled to select one of the DTBCLKs for pipe */
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switch (otg_inst) {
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case 0:
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REG_UPDATE(DPSTREAMCLK_CNTL,
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DPSTREAMCLK_PIPE0_EN, (src == REFCLK) ? 0 : 1);
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break;
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case 1:
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REG_UPDATE(DPSTREAMCLK_CNTL,
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DPSTREAMCLK_PIPE1_EN, (src == REFCLK) ? 0 : 1);
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break;
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case 2:
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REG_UPDATE(DPSTREAMCLK_CNTL,
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DPSTREAMCLK_PIPE2_EN, (src == REFCLK) ? 0 : 1);
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break;
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case 3:
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REG_UPDATE(DPSTREAMCLK_CNTL,
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DPSTREAMCLK_PIPE3_EN, (src == REFCLK) ? 0 : 1);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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void dccg31_enable_symclk32_se(
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struct dccg *dccg,
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int hpo_se_inst,
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enum phyd32clk_clock_source phyd32clk)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* select one of the PHYD32CLKs as the source for symclk32_se */
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switch (hpo_se_inst) {
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case 0:
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REG_UPDATE_2(SYMCLK32_SE_CNTL,
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SYMCLK32_SE0_SRC_SEL, phyd32clk,
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SYMCLK32_SE0_EN, 1);
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break;
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case 1:
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REG_UPDATE_2(SYMCLK32_SE_CNTL,
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SYMCLK32_SE1_SRC_SEL, phyd32clk,
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SYMCLK32_SE1_EN, 1);
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break;
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case 2:
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REG_UPDATE_2(SYMCLK32_SE_CNTL,
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SYMCLK32_SE2_SRC_SEL, phyd32clk,
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SYMCLK32_SE2_EN, 1);
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break;
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case 3:
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REG_UPDATE_2(SYMCLK32_SE_CNTL,
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SYMCLK32_SE3_SRC_SEL, phyd32clk,
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SYMCLK32_SE3_EN, 1);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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void dccg31_disable_symclk32_se(
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struct dccg *dccg,
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int hpo_se_inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* set refclk as the source for symclk32_se */
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switch (hpo_se_inst) {
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case 0:
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REG_UPDATE_2(SYMCLK32_SE_CNTL,
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SYMCLK32_SE0_SRC_SEL, 0,
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SYMCLK32_SE0_EN, 0);
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break;
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case 1:
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REG_UPDATE_2(SYMCLK32_SE_CNTL,
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SYMCLK32_SE1_SRC_SEL, 0,
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SYMCLK32_SE1_EN, 0);
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break;
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case 2:
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REG_UPDATE_2(SYMCLK32_SE_CNTL,
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SYMCLK32_SE2_SRC_SEL, 0,
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SYMCLK32_SE2_EN, 0);
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break;
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case 3:
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REG_UPDATE_2(SYMCLK32_SE_CNTL,
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SYMCLK32_SE3_SRC_SEL, 0,
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SYMCLK32_SE3_EN, 0);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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void dccg31_enable_symclk32_le(
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struct dccg *dccg,
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int hpo_le_inst,
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enum phyd32clk_clock_source phyd32clk)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* select one of the PHYD32CLKs as the source for symclk32_le */
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switch (hpo_le_inst) {
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case 0:
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REG_UPDATE_2(SYMCLK32_LE_CNTL,
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SYMCLK32_LE0_SRC_SEL, phyd32clk,
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SYMCLK32_LE0_EN, 1);
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break;
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case 1:
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REG_UPDATE_2(SYMCLK32_LE_CNTL,
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SYMCLK32_LE1_SRC_SEL, phyd32clk,
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SYMCLK32_LE1_EN, 1);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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void dccg31_disable_symclk32_le(
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struct dccg *dccg,
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int hpo_le_inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* set refclk as the source for symclk32_le */
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switch (hpo_le_inst) {
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case 0:
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REG_UPDATE_2(SYMCLK32_LE_CNTL,
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SYMCLK32_LE0_SRC_SEL, 0,
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SYMCLK32_LE0_EN, 0);
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break;
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case 1:
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REG_UPDATE_2(SYMCLK32_LE_CNTL,
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SYMCLK32_LE1_SRC_SEL, 0,
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SYMCLK32_LE1_EN, 0);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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void dccg31_set_physymclk(
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struct dccg *dccg,
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int phy_inst,
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@ -241,12 +390,25 @@ static void dccg31_set_dispclk_change_mode(
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void dccg31_init(struct dccg *dccg)
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{
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/* Set HPO stream encoder to use refclk to avoid case where PHY is
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* disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which
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* will cause DCN to hang.
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*/
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dccg31_disable_symclk32_se(dccg, 0);
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dccg31_disable_symclk32_se(dccg, 1);
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dccg31_disable_symclk32_se(dccg, 2);
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dccg31_disable_symclk32_se(dccg, 3);
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}
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static const struct dccg_funcs dccg31_funcs = {
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.update_dpp_dto = dccg2_update_dpp_dto,
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.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
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.dccg_init = dccg31_init,
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.set_dpstreamclk = dccg31_set_dpstreamclk,
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.enable_symclk32_se = dccg31_enable_symclk32_se,
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.disable_symclk32_se = dccg31_disable_symclk32_se,
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.enable_symclk32_le = dccg31_enable_symclk32_le,
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.disable_symclk32_le = dccg31_disable_symclk32_le,
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.set_physymclk = dccg31_set_physymclk,
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.set_dtbclk_dto = dccg31_set_dtbclk_dto,
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.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
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@ -130,6 +130,24 @@ struct dccg *dccg31_create(
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void dccg31_init(struct dccg *dccg);
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void dccg31_enable_symclk32_se(
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struct dccg *dccg,
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int hpo_se_inst,
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enum phyd32clk_clock_source phyd32clk);
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void dccg31_disable_symclk32_se(
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struct dccg *dccg,
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int hpo_se_inst);
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void dccg31_enable_symclk32_le(
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struct dccg *dccg,
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int hpo_le_inst,
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enum phyd32clk_clock_source phyd32clk);
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void dccg31_disable_symclk32_le(
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struct dccg *dccg,
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int hpo_le_inst);
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void dccg31_set_physymclk(
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struct dccg *dccg,
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int phy_inst,
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@ -79,7 +79,30 @@ struct dccg_funcs {
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void (*otg_drop_pixel)(struct dccg *dccg,
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uint32_t otg_inst);
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void (*dccg_init)(struct dccg *dccg);
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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void (*set_dpstreamclk)(
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struct dccg *dccg,
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enum hdmistreamclk_source src,
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int otg_inst);
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void (*enable_symclk32_se)(
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struct dccg *dccg,
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int hpo_se_inst,
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enum phyd32clk_clock_source phyd32clk);
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void (*disable_symclk32_se)(
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struct dccg *dccg,
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int hpo_se_inst);
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void (*enable_symclk32_le)(
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struct dccg *dccg,
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int hpo_le_inst,
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enum phyd32clk_clock_source phyd32clk);
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void (*disable_symclk32_le)(
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struct dccg *dccg,
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int hpo_le_inst);
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#endif
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void (*set_physymclk)(
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struct dccg *dccg,
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int phy_inst,
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@ -100,6 +100,9 @@ enum crc_selection {
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enum otg_out_mux_dest {
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OUT_MUX_DIO = 0,
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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OUT_MUX_HPO_DP = 2,
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#endif
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};
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enum h_timing_div_mode {
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