d76b12da98
HW Blocks:
+--------+ +-----+ +------+
| OPTC | | HDA | | HUBP |
+--------+ +-----+ +------+
| | |
| | |
HPO ====|==========|========|====
| | v |
| | +-----+ |
| | | APG | |
| | +-----+ |
| | | |
| v v v
| +---------------------+
| | HPO Stream Encoder |
| +---------------------+
| |
| v
| +--------------------+
| | HPO Link Encoder |
| +--------------------+
| |
v ===============|=============
v
+------------------+
| DIO Output Mux |
+------------------+
|
v
+-----+
| PHY |
+-----+
| PHYD32CLK[0]
v
+------+
| DCCG |
+------+
|
v
SYMCLK32
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
129 lines
3.6 KiB
C
129 lines
3.6 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_DCCG_H__
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#define __DAL_DCCG_H__
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#include "dc_types.h"
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#include "hw_shared.h"
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enum phyd32clk_clock_source {
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PHYD32CLKA,
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PHYD32CLKB,
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PHYD32CLKC,
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PHYD32CLKD,
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PHYD32CLKE,
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PHYD32CLKF,
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PHYD32CLKG,
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};
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enum physymclk_clock_source {
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PHYSYMCLK_FORCE_SRC_SYMCLK, // Select symclk as source of clock which is output to PHY through DCIO.
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PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO.
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PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
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};
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enum hdmistreamclk_source {
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REFCLK, // Selects REFCLK as source for hdmistreamclk.
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DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk.
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};
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enum dentist_dispclk_change_mode {
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DISPCLK_CHANGE_MODE_IMMEDIATE,
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DISPCLK_CHANGE_MODE_RAMPING,
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};
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struct dccg {
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struct dc_context *ctx;
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const struct dccg_funcs *funcs;
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int pipe_dppclk_khz[MAX_PIPES];
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int ref_dppclk;
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int dtbclk_khz[MAX_PIPES];
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int audio_dtbclk_khz;
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int ref_dtbclk_khz;
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};
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struct dccg_funcs {
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void (*update_dpp_dto)(struct dccg *dccg,
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int dpp_inst,
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int req_dppclk);
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void (*get_dccg_ref_freq)(struct dccg *dccg,
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unsigned int xtalin_freq_inKhz,
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unsigned int *dccg_ref_freq_inKhz);
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void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
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bool en);
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void (*otg_add_pixel)(struct dccg *dccg,
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uint32_t otg_inst);
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void (*otg_drop_pixel)(struct dccg *dccg,
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uint32_t otg_inst);
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void (*dccg_init)(struct dccg *dccg);
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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void (*set_dpstreamclk)(
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struct dccg *dccg,
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enum hdmistreamclk_source src,
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int otg_inst);
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void (*enable_symclk32_se)(
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struct dccg *dccg,
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int hpo_se_inst,
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enum phyd32clk_clock_source phyd32clk);
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void (*disable_symclk32_se)(
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struct dccg *dccg,
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int hpo_se_inst);
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void (*enable_symclk32_le)(
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struct dccg *dccg,
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int hpo_le_inst,
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enum phyd32clk_clock_source phyd32clk);
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void (*disable_symclk32_le)(
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struct dccg *dccg,
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int hpo_le_inst);
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#endif
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void (*set_physymclk)(
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struct dccg *dccg,
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int phy_inst,
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enum physymclk_clock_source clk_src,
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bool force_enable);
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void (*set_dtbclk_dto)(
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struct dccg *dccg,
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int dtbclk_inst,
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int req_dtbclk_khz,
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int num_odm_segments,
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const struct dc_crtc_timing *timing);
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void (*set_audio_dtbclk_dto)(
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struct dccg *dccg,
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uint32_t req_audio_dtbclk_khz);
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void (*set_dispclk_change_mode)(
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struct dccg *dccg,
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enum dentist_dispclk_change_mode change_mode);
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};
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#endif //__DAL_DCCG_H__
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