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RISC-V Devicetrees for v6.8

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StarFive:
 Key peripheral support for the jh7100 that depended on the non-standard
 non-coherent DMA operations, namely mmc, sdcard and sdio wifi. This
 platform has long been supported out of tree by Emil and Ubuntu etc ship
 images for it, so having mainline support for a wider range of
 peripherals (at last) is great.
 
 Microchip:
 The flash used by Auto Update support and the corresponding QSPI
 controller are added. On publicly available Icicle kits this flash is
 not usable (engineering sample silicon issues) but in the future Icicle
 kits will be available that have production silicon.
 
 T-Head:
 Jisheng is busy with RL this cycle and hence T-Head appears here. The
 Lichee Pi and BeagleV both grow eMMC and uSD support.
 
 Sopgho:
 Support for the Huashan Pi and the cv1812h SoC it uses. The cv1812h is
 almost identical to the existing cv1800b SoC. These SoCs are intended
 for use in IP camera type systems but also appear on SBCs, with the last
 digit denoting the amount integrated DDR3 the device has. The difference
 between the cv1812h and the existing cv180x devices appears to be the
 addition of video output interfaces.
 
 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Merge tag 'riscv-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

RISC-V Devicetrees for v6.8

StarFive:
Key peripheral support for the jh7100 that depended on the non-standard
non-coherent DMA operations, namely mmc, sdcard and sdio wifi. This
platform has long been supported out of tree by Emil and Ubuntu etc ship
images for it, so having mainline support for a wider range of
peripherals (at last) is great.

Microchip:
The flash used by Auto Update support and the corresponding QSPI
controller are added. On publicly available Icicle kits this flash is
not usable (engineering sample silicon issues) but in the future Icicle
kits will be available that have production silicon.

T-Head:
Jisheng is busy with RL this cycle and hence T-Head appears here. The
Lichee Pi and BeagleV both grow eMMC and uSD support.

Sopgho:
Support for the Huashan Pi and the cv1812h SoC it uses. The cv1812h is
almost identical to the existing cv1800b SoC. These SoCs are intended
for use in IP camera type systems but also appear on SBCs, with the last
digit denoting the amount integrated DDR3 the device has. The difference
between the cv1812h and the existing cv180x devices appears to be the
addition of video output interfaces.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: Enable SDIO wifi on JH7100 boards
  riscv: dts: starfive: Enable SD-card on JH7100 boards
  riscv: dts: starfive: Add JH7100 MMC nodes
  riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards
  riscv: dts: starfive: Add JH7100 cache controller
  riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs
  riscv: dts: starfive: Group tuples in interrupt properties
  riscv: dts: thead: Enable LicheePi 4A eMMC and microSD
  riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD
  riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock
  riscv: dts: microchip: add the mpfs' system controller qspi & associated flash
  riscv: dts: sophgo: add Huashan Pi board device tree
  riscv: dts: sophgo: add initial CV1812H SoC device tree
  riscv: dts: sophgo: cv18xx: Add gpio devices
  riscv: dts: sophgo: Separate compatible specific for CV1800B soc
  dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
  dt-bindings: timer: Add SOPHGO CV1812H clint
  dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic

Link: https://lore.kernel.org/r/20231221-skimmed-boxy-b78aed8afdc4@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-12-21 17:09:34 +00:00
commit dd93766396
15 changed files with 568 additions and 118 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
View File

@ -66,6 +66,7 @@ properties:
- enum:
- allwinner,sun20i-d1-plic
- sophgo,cv1800b-plic
- sophgo,cv1812h-plic
- sophgo,sg2042-plic
- thead,th1520-plic
- const: thead,c900-plic

4
Documentation/devicetree/bindings/riscv/sophgo.yaml
View File

@ -22,6 +22,10 @@ properties:
- enum:
- milkv,duo
- const: sophgo,cv1800b
- items:
- enum:
- sophgo,huashan-pi
- const: sophgo,cv1812h
- items:
- enum:
- milkv,pioneer

1
Documentation/devicetree/bindings/timer/sifive,clint.yaml
View File

@ -38,6 +38,7 @@ properties:
- enum:
- allwinner,sun20i-d1-clint
- sophgo,cv1800b-clint
- sophgo,cv1812h-clint
- thead,th1520-clint
- const: thead,c900-clint
- items:

21
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
View File

@ -199,6 +199,27 @@
status = "okay";
};
&syscontroller_qspi {
/*
* The flash *is* there, but Icicle kits that have engineering sample
* silicon (write?) access to this flash to non-functional. The system
* controller itself can actually access it, but the MSS cannot write
* an image there. Instantiating a coreQSPI in the fabric & connecting
* it to the flash instead should work though. Pre-production or later
* silicon does not have this issue.
*/
status = "disabled";
sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
spi-rx-bus-width = <1>;
reg = <0>;
};
};
&usb {
status = "okay";
dr_mode = "host";

17
arch/riscv/boot/dts/microchip/mpfs.dtsi
View File

@ -193,6 +193,12 @@
mboxes = <&mbox 0>;
};
scbclk: mssclkclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <80000000>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
@ -523,5 +529,16 @@
#mbox-cells = <1>;
status = "disabled";
};
syscontroller_qspi: spi@37020100 {
compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x37020100 0x0 0x100>;
interrupt-parent = <&plic>;
interrupts = <110>;
clocks = <&scbclk>;
status = "disabled";
};
};
};

1
arch/riscv/boot/dts/sophgo/Makefile
View File

@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb

123
arch/riscv/boot/dts/sophgo/cv1800b.dtsi
View File

@ -3,121 +3,16 @@
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "cv18xx.dtsi"
/ {
compatible = "sophgo,cv1800b";
#address-cells = <1>;
#size-cells = <1>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_25m";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <1>;
#size-cells = <1>;
dma-noncoherent;
ranges;
uart0: serial@4140000 {
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@4150000 {
compatible = "snps,dw-apb-uart";
reg = <0x04150000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@4160000 {
compatible = "snps,dw-apb-uart";
reg = <0x04160000 0x100>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@4170000 {
compatible = "snps,dw-apb-uart";
reg = <0x04170000 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart4: serial@41c0000 {
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
plic: interrupt-controller@70000000 {
compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};
&plic {
compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
};
&clint {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
};

48
arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts Normal file
View File

@ -0,0 +1,48 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
/dts-v1/;
#include "cv1812h.dtsi"
/ {
model = "Huashan Pi";
compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
coprocessor_rtos: region@8fe00000 {
reg = <0x8fe00000 0x200000>;
no-map;
};
};
};
&osc {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};

24
arch/riscv/boot/dts/sophgo/cv1812h.dtsi Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "cv18xx.dtsi"
/ {
compatible = "sophgo,cv1812h";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
};
&plic {
compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
};
&clint {
compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
};

193
arch/riscv/boot/dts/sophgo/cv18xx.dtsi Normal file
View File

@ -0,0 +1,193 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_25m";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <1>;
#size-cells = <1>;
dma-noncoherent;
ranges;
gpio0: gpio@3020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio1: gpio@3021000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3021000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio2: gpio@3022000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3022000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio3: gpio@3023000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3023000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
portd: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
};
};
uart0: serial@4140000 {
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@4150000 {
compatible = "snps,dw-apb-uart";
reg = <0x04150000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@4160000 {
compatible = "snps,dw-apb-uart";
reg = <0x04160000 0x100>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@4170000 {
compatible = "snps,dw-apb-uart";
reg = <0x04170000 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart4: serial@41c0000 {
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
plic: interrupt-controller@70000000 {
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};

131
arch/riscv/boot/dts/starfive/jh7100-common.dtsi
View File

@ -12,6 +12,8 @@
/ {
aliases {
mmc0 = &sdio0;
mmc1 = &sdio1;
serial0 = &uart3;
};
@ -39,6 +41,35 @@
label = "ack";
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-reserved@fa000000 {
reg = <0x0 0xfa000000 0x0 0x1000000>;
no-map;
};
linux,dma@107a000000 {
compatible = "shared-dma-pool";
reg = <0x10 0x7a000000 0x0 0x1000000>;
no-map;
linux,dma-default;
};
};
soc {
dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>,
<0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>,
<0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>;
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
};
};
&gpio {
@ -84,6 +115,78 @@
};
};
sdio0_pins: sdio0-0 {
clk-pins {
pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
sdio-pins {
pinmux = <GPIOMUX(55, GPO_LOW, GPO_DISABLE,
GPI_SDIO0_PAD_CARD_DETECT_N)>,
<GPIOMUX(53,
GPO_SDIO0_PAD_CCMD_OUT,
GPO_SDIO0_PAD_CCMD_OEN,
GPI_SDIO0_PAD_CCMD_IN)>,
<GPIOMUX(49,
GPO_SDIO0_PAD_CDATA_OUT_BIT0,
GPO_SDIO0_PAD_CDATA_OEN_BIT0,
GPI_SDIO0_PAD_CDATA_IN_BIT0)>,
<GPIOMUX(50,
GPO_SDIO0_PAD_CDATA_OUT_BIT1,
GPO_SDIO0_PAD_CDATA_OEN_BIT1,
GPI_SDIO0_PAD_CDATA_IN_BIT1)>,
<GPIOMUX(51,
GPO_SDIO0_PAD_CDATA_OUT_BIT2,
GPO_SDIO0_PAD_CDATA_OEN_BIT2,
GPI_SDIO0_PAD_CDATA_IN_BIT2)>,
<GPIOMUX(52,
GPO_SDIO0_PAD_CDATA_OUT_BIT3,
GPO_SDIO0_PAD_CDATA_OEN_BIT3,
GPI_SDIO0_PAD_CDATA_IN_BIT3)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
};
sdio1_pins: sdio1-0 {
clk-pins {
pinmux = <GPIOMUX(33, GPO_SDIO1_PAD_CCLK_OUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
sdio-pins {
pinmux = <GPIOMUX(29,
GPO_SDIO1_PAD_CCMD_OUT,
GPO_SDIO1_PAD_CCMD_OEN,
GPI_SDIO1_PAD_CCMD_IN)>,
<GPIOMUX(36,
GPO_SDIO1_PAD_CDATA_OUT_BIT0,
GPO_SDIO1_PAD_CDATA_OEN_BIT0,
GPI_SDIO1_PAD_CDATA_IN_BIT0)>,
<GPIOMUX(30,
GPO_SDIO1_PAD_CDATA_OUT_BIT1,
GPO_SDIO1_PAD_CDATA_OEN_BIT1,
GPI_SDIO1_PAD_CDATA_IN_BIT1)>,
<GPIOMUX(34,
GPO_SDIO1_PAD_CDATA_OUT_BIT2,
GPO_SDIO1_PAD_CDATA_OEN_BIT2,
GPI_SDIO1_PAD_CDATA_IN_BIT2)>,
<GPIOMUX(31,
GPO_SDIO1_PAD_CDATA_OUT_BIT3,
GPO_SDIO1_PAD_CDATA_OEN_BIT3,
GPI_SDIO1_PAD_CDATA_IN_BIT3)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
};
uart3_pins: uart3-0 {
rx-pins {
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
@ -154,6 +257,34 @@
clock-frequency = <27000000>;
};
&sdio0 {
broken-cd;
bus-width = <4>;
cap-sd-highspeed;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_pins>;
status = "okay";
};
&sdio1 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
cap-power-off-card;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio1_pins>;
status = "okay";
wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;

48
arch/riscv/boot/dts/starfive/jh7100.dtsi
View File

@ -32,6 +32,7 @@
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
@ -60,6 +61,7 @@
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
@ -144,26 +146,64 @@
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
dma-noncoherent;
ranges;
clint: clint@2000000 {
compatible = "starfive,jh7100-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>;
};
ccache: cache-controller@2010000 {
compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
reg = <0x0 0x2010000 0x0 0x1000>;
interrupts = <128>, <130>, <131>, <129>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <2097152>;
cache-unified;
};
plic: interrupt-controller@c000000 {
compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
&cpu1_intc 11 &cpu1_intc 9>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
<&cpu1_intc 11>, <&cpu1_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
riscv,ndev = <133>;
};
sdio0: mmc@10000000 {
compatible = "snps,dw-mshc";
reg = <0x0 0x10000000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
<&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
clock-names = "biu", "ciu";
interrupts = <4>;
data-addr = <0>;
fifo-depth = <32>;
fifo-watermark-aligned;
status = "disabled";
};
sdio1: mmc@10010000 {
compatible = "snps,dw-mshc";
reg = <0x0 0x10010000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
<&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
clock-names = "biu", "ciu";
interrupts = <5>;
data-addr = <0>;
fifo-depth = <32>;
fifo-watermark-aligned;
status = "disabled";
};
clkgen: clock-controller@11800000 {
compatible = "starfive,jh7100-clkgen";
reg = <0x0 0x11800000 0x0 0x10000>;

20
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
View File

@ -48,6 +48,10 @@
clock-frequency = <62500000>;
};
&sdhci_clk {
clock-frequency = <198000000>;
};
&uart_sclk {
clock-frequency = <100000000>;
};
@ -56,6 +60,22 @@
status = "okay";
};
&emmc {
bus-width = <8>;
max-frequency = <198000000>;
mmc-hs400-1_8v;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&sdio0 {
bus-width = <4>;
max-frequency = <198000000>;
status = "okay";
};
&uart0 {
status = "okay";
};

20
arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
View File

@ -29,6 +29,10 @@
clock-frequency = <62500000>;
};
&sdhci_clk {
clock-frequency = <198000000>;
};
&uart_sclk {
clock-frequency = <100000000>;
};
@ -36,3 +40,19 @@
&dmac0 {
status = "okay";
};
&emmc {
bus-width = <8>;
max-frequency = <198000000>;
mmc-hs400-1_8v;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&sdio0 {
bus-width = <4>;
max-frequency = <198000000>;
status = "okay";
};

34
arch/riscv/boot/dts/thead/th1520.dtsi
View File

@ -146,6 +146,13 @@
#clock-cells = <0>;
};
sdhci_clk: sdhci-clock {
compatible = "fixed-clock";
clock-frequency = <198000000>;
clock-output-names = "sdhci_clk";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@ -304,6 +311,33 @@
status = "disabled";
};
emmc: mmc@ffe7080000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe7080000 0x0 0x10000>;
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdhci_clk>;
clock-names = "core";
status = "disabled";
};
sdio0: mmc@ffe7090000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe7090000 0x0 0x10000>;
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdhci_clk>;
clock-names = "core";
status = "disabled";
};
sdio1: mmc@ffe70a0000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe70a0000 0x0 0x10000>;
interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdhci_clk>;
clock-names = "core";
status = "disabled";
};
timer0: timer@ffefc32000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32000 0x0 0x14>;