iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/i915/ipc: move IPC debugfs to skl_watermark.c

Browse Source 
Follow the new direction for debugfs files, moving the details where the
implementation is. It seems quite natural skl_watermark.c is the place
that controls IPC details, even for debugfs, not
intel_display_debugfs.c.

Rename the functions and convert dev_priv->i915 while at it.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/9d59b18f5dc06e86a48c1ce0f40d625f51e3e85a.1662983005.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2022-09-12 14:45:13 +03:00
parent 23fbdb07d6
commit dde01ed5b0
3 changed files with 63 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
drivers/gpu/drm/i915/display/intel_display_debugfs.c
View File

@ -983,58 +983,6 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
return 0;
}
static int i915_ipc_status_show(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = m->private;
seq_printf(m, "Isochronous Priority Control: %s\n",
str_yes_no(skl_watermark_ipc_enabled(dev_priv)));
return 0;
}
static int i915_ipc_status_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *dev_priv = inode->i_private;
if (!HAS_IPC(dev_priv))
return -ENODEV;
return single_open(file, i915_ipc_status_show, dev_priv);
}
static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
size_t len, loff_t *offp)
{
struct seq_file *m = file->private_data;
struct drm_i915_private *dev_priv = m->private;
intel_wakeref_t wakeref;
bool enable;
int ret;
ret = kstrtobool_from_user(ubuf, len, &enable);
if (ret < 0)
return ret;
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
if (!skl_watermark_ipc_enabled(dev_priv) && enable)
drm_info(&dev_priv->drm,
"Enabling IPC: WM will be proper only after next commit\n");
dev_priv->ipc_enabled = enable;
skl_watermark_ipc_update(dev_priv);
}
return len;
}
static const struct file_operations i915_ipc_status_fops = {
.owner = THIS_MODULE,
.open = i915_ipc_status_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
.write = i915_ipc_status_write
};
static int i915_ddb_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@ -1911,7 +1859,6 @@ static const struct {
{"i915_dp_test_active", &i915_displayport_test_active_fops},
{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
{"i915_hpd_short_storm_ctl", &i915_hpd_short_storm_ctl_fops},
{"i915_ipc_status", &i915_ipc_status_fops},
{"i915_drrs_ctl", &i915_drrs_ctl_fops},
{"i915_edp_psr_debug", &i915_edp_psr_debug_fops},
};
@ -1935,6 +1882,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
intel_dmc_debugfs_register(i915);
intel_fbc_debugfs_register(i915);
skl_watermark_ipc_debugfs_register(i915);
}
static int i915_panel_show(struct seq_file *m, void *data)

61
drivers/gpu/drm/i915/display/skl_watermark.c
View File

@ -3471,3 +3471,64 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), val);
}
}
static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)
{
struct drm_i915_private *i915 = m->private;
seq_printf(m, "Isochronous Priority Control: %s\n",
str_yes_no(skl_watermark_ipc_enabled(i915)));
return 0;
}
static int skl_watermark_ipc_status_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
if (!HAS_IPC(i915))
return -ENODEV;
return single_open(file, skl_watermark_ipc_status_show, i915);
}
static ssize_t skl_watermark_ipc_status_write(struct file *file,
const char __user *ubuf,
size_t len, loff_t *offp)
{
struct seq_file *m = file->private_data;
struct drm_i915_private *i915 = m->private;
intel_wakeref_t wakeref;
bool enable;
int ret;
ret = kstrtobool_from_user(ubuf, len, &enable);
if (ret < 0)
return ret;
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
if (!skl_watermark_ipc_enabled(i915) && enable)
drm_info(&i915->drm,
"Enabling IPC: WM will be proper only after next commit\n");
i915->ipc_enabled = enable;
skl_watermark_ipc_update(i915);
}
return len;
}
static const struct file_operations skl_watermark_ipc_status_fops = {
.owner = THIS_MODULE,
.open = skl_watermark_ipc_status_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
.write = skl_watermark_ipc_status_write
};
void skl_watermark_ipc_debugfs_register(struct drm_i915_private *i915)
{
struct drm_minor *minor = i915->drm.primary;
debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, i915,
&skl_watermark_ipc_status_fops);
}

1
drivers/gpu/drm/i915/display/skl_watermark.h
View File

@ -47,6 +47,7 @@ void intel_wm_state_verify(struct intel_crtc *crtc,
void skl_watermark_ipc_init(struct drm_i915_private *i915);
void skl_watermark_ipc_update(struct drm_i915_private *i915);
bool skl_watermark_ipc_enabled(struct drm_i915_private *i915);
void skl_watermark_ipc_debugfs_register(struct drm_i915_private *i915);
void skl_wm_init(struct drm_i915_private *i915);